f'ing thing still won't work.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
ed9f18d545
commit
4fa89208a1
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@ -19,8 +19,8 @@
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/* converted to C 6/2004 yhlu */
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#define DEBUG_RAM_CONFIG 1
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#define ASM_CONSOLE_LOGLEVEL 10
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#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 0))
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#define ASM_CONSOLE_LOGLEVEL 9
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#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 1))
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/* DDR DIMM Mode register Definitions */
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@ -46,6 +46,7 @@
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//#define CAS_LATENCY CAS_2_5
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//#define CAS_LATENCY CAS_1_5
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/* WOW! this could be bad! sets casl to 2 without checking! */
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#define MRS_VALUE (MODE_NORM | CAS_LATENCY | BURST_TYPE | BURST_LENGTH)
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#define EMRS_VALUE 0x000
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@ -73,12 +74,19 @@ static inline void do_ram_command (const struct mem_controller *ctrl, uint32_t v
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/* %ecx - initial address to read from */
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/* Compute the offset */
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dword = value >> 16;
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for(i=0;i<8;i++) {
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// for(i=0;i<4;i++) {
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for(i=0;i<1;i++) {
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/* Set the ram command */
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byte = pci_read_config8(ctrl->d0, 0x7c);
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byte = pci_read_config8(ctrl->d0, 0x70);
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byte &= 0x8f;
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byte |= (uint8_t)(value & 0xff);
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pci_write_config8(ctrl->d0, 0x7c, byte);
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#if DEBUG_RAM_CONFIG
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print_debug("R:");
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print_debug_hex8(byte);
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print_debug("\r\n");
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#endif
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pci_write_config8(ctrl->d0, 0x70, byte);
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/* Assert the command to the memory */
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#if DEBUG_RAM_CONFIG >= 2
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@ -89,15 +97,17 @@ static inline void do_ram_command (const struct mem_controller *ctrl, uint32_t v
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result = read32(dword);
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#if DEBUG_RAM_CONFIG
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print_debug("Done\r\n");
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#endif
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/* Go to the next base address */
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dword += 0x04000000;
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dword += 0x0200000;
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}
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/* The command has been sent to all dimms so get out */
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}
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static inline void RAM_CMD(const struct mem_controller *ctrl, uint32_t command, uint32_t offset) {
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uint32_t value = ((offset) << (MD_SHIFT + 16))|((command << 4) & 0x70) ;
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do_ram_command(ctrl, value);
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@ -116,10 +126,10 @@ static inline void ram_mrs(const struct mem_controller *ctrl, uint32_t value){
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/* Read the cas latency setting */
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uint8_t byte;
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uint32_t dword;
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byte = pci_read_config8(ctrl->d0, 0x78);
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byte = pci_read_config8(ctrl->d0, 0x60);
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/* Transform it into the form expected by SDRAM */
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dword = ram_cas_latency[(byte>>4) & 3];
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dword = ram_cas_latency[(byte>>5) & 1];
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#warning RAM_MRS -- using BROKEN hard-wired CAS 2.0. FIX ME SOON
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value |= (dword<<(16+MD_SHIFT));
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value |= (MODE_NORM | BURST_TYPE | BURST_LENGTH) << (16+MD_SHIFT);
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@ -131,10 +141,10 @@ static inline void ram_mrs(const struct mem_controller *ctrl, uint32_t value){
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static void RAM_NORMAL(const struct mem_controller *ctrl) {
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uint8_t byte;
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byte = pci_read_config8(ctrl->d0, 0x7c);
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byte = pci_read_config8(ctrl->d0, 0x70);
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byte &= 0x8f;
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byte |= (RAM_COMMAND_NORMAL << 4);
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pci_write_config8(ctrl->d0, 0x7c, byte);
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pci_write_config8(ctrl->d0, 0x70, byte);
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}
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static void RAM_RESET_DDR_PTR(const struct mem_controller *ctrl) {
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@ -150,9 +160,9 @@ static void RAM_RESET_DDR_PTR(const struct mem_controller *ctrl) {
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static void ENABLE_REFRESH(const struct mem_controller *ctrl)
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{
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uint32_t dword;
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dword = pci_read_config32(ctrl->d0, 0x7c);
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dword = pci_read_config32(ctrl->d0, 0x70);
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dword |= (1 << 29);
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pci_write_config32(ctrl->d0, 0x7c, dword);
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pci_write_config32(ctrl->d0, 0x70, dword);
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}
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/*
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@ -279,8 +289,8 @@ static const long register_values[] = {
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* 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
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* 11 == Normal (All Access go to DRAM)
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*/
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0x90, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
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0x94, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
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// 0x90, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
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//0x94, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
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/* FIXME why was I attempting to set a reserved bit? */
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@ -330,6 +340,8 @@ static const long register_values[] = {
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* [00:00] DRAM type --hardwired to 1 to indicate DDR
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*/
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0x70, 0xdf0f6c7f, 0,
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/* undocumnted shit */
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0x80, 0, 0xaf0031,
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};
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@ -347,25 +359,6 @@ static const long register_values[] = {
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* Which are a triple of configuration regiser, mask, and value.
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*
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*/
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/* from 1M or 512K */
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#define RCOMP_MMIO 0x100000
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/* DDR RECOMP table */
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static const long ddr_rcomp_1[] = {
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0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
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0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
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};
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static const long ddr_rcomp_2[] = {
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0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
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0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
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};
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static const long ddr_rcomp_3[] = {
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0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0x88888888, 0x88888888, 0x88888888, 0x88888888,
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};
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#define rcomp_init_str "Setting RCOMP registers.\r\n"
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static void write_8dwords(uint32_t src_addr, uint32_t dst_addr) {
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int i;
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@ -382,90 +375,6 @@ static void write_8dwords(uint32_t src_addr, uint32_t dst_addr) {
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//#define SLOW_DOWN_IO inb(0x80);
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#define SLOW_DOWN_IO udelay(40);
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static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
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uint32_t dword;
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#if DEBUG_RAM_CONFIG
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print_debug(rcomp_init_str);
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#endif
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/*enable access to the rcomp bar */
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/* for e7501 they also set bit 31 ... */
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dword = pci_read_config32(ctrl->d0, 0x0f4);
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dword |= 1<<22;
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pci_write_config32(ctrl->d0, 0x0f4, dword);
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/* Set the MMIO address to 512K */
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pci_write_config32(ctrl->d0, 0x14, RCOMP_MMIO);
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dword = read32(RCOMP_MMIO + 0x20);
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dword |= (1<<9);
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write32(RCOMP_MMIO + 0x20, dword);
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#ifdef NOTNOW
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/* Begin to write the RCOMP registers */
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write8(RCOMP_MMIO + 0x2c, 0xff);
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write32(RCOMP_MMIO + 0x30, 0x01040444);
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write8(RCOMP_MMIO + 0x34, 0x04);
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write32(RCOMP_MMIO + 0x40, 0);
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write16(RCOMP_MMIO + 0x44, 0);
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write16(RCOMP_MMIO + 0x48, 0);
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write16(RCOMP_MMIO + 0x50, 0);
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write_8dwords((uint32_t)ddr_rcomp_1, RCOMP_MMIO + 0x60);
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write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x80);
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write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0xa0);
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write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x140);
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write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x1c0);
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write_8dwords((uint32_t)ddr_rcomp_3, RCOMP_MMIO + 0x180);
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#if 0 /* Print the RCOMP registers */
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movl $RCOMP_MMIO, %ecx
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1: movl %ecx, %eax
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andb $0x0f, %al
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jnz 2f
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CONSOLE_INFO_TX_CHAR($'\r')
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CONSOLE_INFO_TX_CHAR($'\n')
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CONSOLE_INFO_TX_HEX32(%ecx)
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CONSOLE_INFO_TX_CHAR($' ')
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CONSOLE_INFO_TX_CHAR($'-')
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CONSOLE_INFO_TX_CHAR($' ')
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2: movl (%ecx), %eax
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CONSOLE_INFO_TX_HEX32(%eax)
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CONSOLE_INFO_TX_CHAR($' ')
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addl $4, %ecx
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cmpl $(RCOMP_MMIO + 0x1e0), %ecx
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jnz 1b
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CONSOLE_INFO_TX_CHAR($'\r')
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CONSOLE_INFO_TX_CHAR($'\n')
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#endif
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dword = read32(RCOMP_MMIO + 0x20);
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dword &= ~(3);
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dword |= 1;
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write32(RCOMP_MMIO + 0x20, dword);
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/* Wait 40 usec */
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SLOW_DOWN_IO;
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/* unblock updates */
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dword = read32(RCOMP_MMIO + 0x20);
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dword &= ~(1<<9);
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write32(RCOMP_MMIO+0x20, dword);
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dword |= (1<<8);
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write32(RCOMP_MMIO+0x20, dword);
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dword &= ~(1<<8);
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write32(RCOMP_MMIO+0x20, dword);
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/* Wait 40 usec */
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SLOW_DOWN_IO;
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#endif
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/*disable access to the rcomp bar */
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dword = pci_read_config32(ctrl->d0, 0x0f4);
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dword &= ~(1<<22);
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pci_write_config32(ctrl->d0, 0x0f4, dword);
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}
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static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
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#if DEBUG_RAM_CONFIG
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@ -494,7 +403,6 @@ static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
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#endif
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}
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static void sdram_set_registers(const struct mem_controller *ctrl){
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// ram_set_rcomp_regs(ctrl);
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ram_set_d0f0_regs(ctrl);
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}
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@ -677,6 +585,23 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
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* a multiple of 4MB. The way we do it now we can size both
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* sides of an assymetric dimm.
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*/
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/* the hell with that! just use byte 31 -- rgm */
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value = spd_read_byte(device, 31); /* size * 4 MB */
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value = log2(value);
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/* this is in 4 MB chunks, or 32 MBits chunks.
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* log base 2 of 32 Mbits is log2 of (32*1024*1024) is 25
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* so add 25
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*/
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value += 25;
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sz.side1 = value;
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sz.side2 = 0;
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#if DEBUG_RAM_CONFIG
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print_debug("returned size log 2 in bits is :");
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print_debug_hex32(value);
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print_debug("\r\n");
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#endif
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goto out;
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#if 0
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value = spd_read_byte(device, 3); /* rows */
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if (value < 0) goto hw_err;
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// if ((value & 0xf) == 0) goto val_err;
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@ -727,6 +652,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
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sz.side2 += ((value >> 4) & 0x0f); /* Add in columsn on side 2 */
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goto out;
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#endif
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val_err:
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die("Bad SPD value\r\n");
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/* If an hw_error occurs report that I have no memory */
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@ -1249,7 +1175,7 @@ static const uint16_t cas_latency_80_4dimms[] = {
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static const uint8_t cas_latency_78[] = {
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DRT_CAS_1_5, DRT_CAS_2_0, DRT_CAS_2_5
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DRT_CAS_2_0, DRT_CAS_2_5
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};
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static long spd_set_cas_latency(const struct mem_controller *ctrl, long dimm_mask) {
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@ -1376,6 +1302,13 @@ static long spd_set_cas_latency(const struct mem_controller *ctrl, long dimm_mas
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}
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static const unsigned int bustimings[8] = {
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/* first four are for GM part */
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266, 200, 200, -1,
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/* and then the GME part */
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266, 200, 200, 333
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};
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static long spd_set_dram_timing(const struct mem_controller *ctrl, long dimm_mask) {
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/* Walk through all dimms and find the interesection of the
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* supported dram timings.
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@ -1385,8 +1318,51 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, long dimm_mas
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uint32_t dword;
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int value;
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/* well, shit. Intel has not seen fit to document the observed
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* setting for these bits. On my chipset it is 3 right now, and
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* that's not in the table documented for this chip.
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* What a shame. We will assume 133 mhz I guess? not sure.
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* also they say in one place it is two bits and in another
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* they say it is 3 bits! we'll assume two bits, that's
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* the only one that makes sense.
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*/
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uint32_t rambusfrequency;
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uint32_t ramindex;
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/* what kind of chip is it? */
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/* only bit that really matters is high order bit ... */
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/* here is a problem with the memory controller struct ...
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* ram control is spread across d0/d1 on this part!
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*/
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ramindex = pci_read_config8(PCI_DEV(0,0,0), 0x44);
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ramindex >>= 5;
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/* compute the index into the table. Use the type of chip
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* as the high order bit and the 0:0.3:c0 & 7 as the low
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* order four bits.
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*/
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ramindex |= pci_read_config8(PCI_DEV(0,0,3), 0xc0) & 7;
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/* we now have an index into the clock rate table ... */
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rambusfrequency = bustimings[ramindex];
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/* Read the inititial state */
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dword = pci_read_config32(ctrl->d0, 0x60);
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#if DEBUG_RAM_CONFIG >= 10
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print_debug("spd_detect_dimms: bus timing index: ");
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print_debug_hex32(ramindex);
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print_debug(" and speed ");
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print_debug_hex32(rambusfrequency);
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print_debug("\r\n");
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#endif
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/* for now, since we are on deadline, set to "known good" and
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* fix later.
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*/
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pci_write_config32(ctrl->d0, 0x60, 0x2a004425);
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return dimm_mask;
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#if 0
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# Intel clears top bit here, should we?
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# No the default is on and for normal timming it should be on. Tom Z
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@ -1394,7 +1370,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, long dimm_mas
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#endif
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HERE. WHat's the frequency kenneth?
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// HERE. WHat's the frequency kenneth?
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for(i = 0; i < DIMM_SOCKETS; i++) {
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if (!(dimm_mask & (1 << i))) {
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continue;
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@ -1515,47 +1491,49 @@ static uint32_t set_dimm_size(const struct mem_controller *ctrl, struct dimm_siz
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uint32_t dch;
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uint8_t byte;
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/* I think size2 is always 0 ... */
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/* Double the size if we are using dual channel memory */
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// if (is_dual_channel(ctrl)) {
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/* Since I have 2 identical channels double the sizes */
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sz.side1++ ;
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sz.side2++;
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// }
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if (sz.side1 != sz.side2) {
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sz.side2 = 0;
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}
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/* Make certain side1 of the dimm is at least 64MB */
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if (sz.side1 >= (25 + 4)) {
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memsz += (1 << (sz.side1 - (25 + 4)) ) ;
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}
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/* Make certain side1 of the dimm is at least 32MB */
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/* This 28 is weird.
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* sz.size1 is log2 size in bits.
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* so what's 28? So think of it as this:
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* in log2 space: 10 + 10 + 8, i.e. 1024 * 1024 * 256 or
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* 256 Mbits, or 32 Mbytes.
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*/
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/* this is from the e7500 code and it's just wrong for small dimes (< 64 MB)
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* However, realistically, this case will never happen! the dimms are all bigger ...
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* so skip the conditional completely.
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* if (sz.side1 >= (28)) { }
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*/
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memsz += (1 << (sz.side1 - (28)) ) ;
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/* Write the size of side 1 of the dimm */
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#if DEBUG_RAM_CONFIG
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print_debug("Write size ");
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print_debug_hex8(memsz);
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print_debug(" to ");
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print_debug_hex8(0x40 + index);
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print_debug("\r\n");
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#endif
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byte = memsz;
|
||||
pci_write_config8(ctrl->d0, 0x60+(index<<1), byte);
|
||||
|
||||
/* Make certain side2 of the dimm is at least 64MB */
|
||||
if (sz.side2 >= (25 + 4)) {
|
||||
memsz += (1 << (sz.side2 - (25 + 4)) ) ;
|
||||
}
|
||||
|
||||
/* Write the size of side 2 of the dimm */
|
||||
byte = memsz;
|
||||
pci_write_config8(ctrl->d0, 0x61+(index<<1), byte);
|
||||
pci_write_config8(ctrl->d0, 0x40+index, byte);
|
||||
|
||||
/* now, fill in DRBs where no physical slot exists */
|
||||
|
||||
for(i=index+1;i<4;i++) {
|
||||
pci_write_config8(ctrl->d0, 0x60+(i<<1),byte);
|
||||
pci_write_config8(ctrl->d0, 0x61+(i<<1),byte);
|
||||
|
||||
pci_write_config8(ctrl->d0, 0x40+i, byte);
|
||||
}
|
||||
|
||||
return memsz;
|
||||
|
||||
}
|
||||
/* LAST_DRB_SLOT is a constant for any E7500 board */
|
||||
#define LAST_DRB_SLOT 0x67
|
||||
|
||||
#define LAST_DRB_SLOT 0x43
|
||||
|
||||
static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
|
||||
{
|
||||
|
|
@ -1582,6 +1560,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
|
|||
}
|
||||
memsz = set_dimm_size(ctrl, sz, memsz, i);
|
||||
}
|
||||
#if 0
|
||||
/* For now hardset everything at 128MB boundaries */
|
||||
/* %ebp has the ram size in multiples of 64MB */
|
||||
// cmpl $0, %ebp /* test if there is no mem - smbus went bad */
|
||||
|
|
@ -1613,6 +1592,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
|
|||
pci_write_config16(ctrl->d0, 0xc8, word);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
return dimm_mask;
|
||||
}
|
||||
|
|
@ -1643,19 +1623,25 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
|
|||
|
||||
if (dimm_mask < 0)
|
||||
goto hw_spd_err;
|
||||
|
||||
/* skip for now until we just get "known good" up
|
||||
dimm_mask = spd_set_cas_latency(ctrl,dimm_mask);
|
||||
dump_pci_device(PCI_DEV(0,0,1));
|
||||
*/
|
||||
|
||||
if (dimm_mask < 0)
|
||||
goto hw_spd_err;
|
||||
dimm_mask = spd_set_dram_timing(ctrl,dimm_mask);
|
||||
if (dimm_mask < 0)
|
||||
goto hw_spd_err;
|
||||
|
||||
#if DEBUG_RAM_CONFIG
|
||||
print_debug(spd_post_init);
|
||||
#endif
|
||||
//moved from dram_post_init
|
||||
spd_set_ram_size(ctrl, dimm_mask);
|
||||
dump_pci_device(PCI_DEV(0,0,1));
|
||||
return;
|
||||
|
||||
hw_spd_err:
|
||||
/* Unrecoverable error reading SPD data */
|
||||
print_err("SPD error - reset\r\n");
|
||||
|
|
@ -1754,42 +1740,26 @@ static void dram_finish(const struct mem_controller *ctrl)
|
|||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
/* Test to see if ECC support is enabled */
|
||||
dword = pci_read_config32(ctrl->d0, 0x7c);
|
||||
dword = pci_read_config32(ctrl->d0, 0x70);
|
||||
dword >>=20;
|
||||
dword &=3;
|
||||
if(dword == 2) {
|
||||
dword &=1;
|
||||
if(dword == 1) {
|
||||
|
||||
#if DEBUG_RAM_CONFIG
|
||||
print_debug(ecc_pre_init);
|
||||
#endif
|
||||
/* Initialize ECC bits , use ECC zero mode (new to 7501)*/
|
||||
pci_write_config8(ctrl->d0, 0x52, 0x06);
|
||||
pci_write_config8(ctrl->d0, 0x52, 0x07);
|
||||
do {
|
||||
byte = pci_read_config8(ctrl->d0, 0x52);
|
||||
|
||||
} while ( (byte & 0x08 ) == 0);
|
||||
|
||||
pci_write_config8(ctrl->d0, 0x52, byte & 0xfc);
|
||||
#if DEBUG_RAM_CONFIG
|
||||
print_debug(ecc_post_init);
|
||||
#endif
|
||||
|
||||
/* Clear the ECC error bits */
|
||||
#if 0
|
||||
pci_write_config8(ctrl->d0f1, 0x80, 0x03); /* dev 0, function 1, offset 80 */
|
||||
pci_write_config8(ctrl->d0f1, 0x82, 0x03); /* dev 0, function 1, offset 82 */
|
||||
|
||||
pci_write_config32(ctrl->d0f1, 0x40, 1<<18); /* clear dev 0, function 1, offset 40; bit 18 by writing a 1 to it */
|
||||
pci_write_config32(ctrl->d0f1, 0x44, 1<<18); /* clear dev 0, function 1, offset 44; bit 18 by writing a 1 to it */
|
||||
#endif
|
||||
pci_write_config8(ctrl->d0, 0x52, 0x0d);
|
||||
}
|
||||
|
||||
/* Clear the ECC error bits */
|
||||
/*
|
||||
dword = pci_read_config32(ctrl->d0, 0x7c); /* FCS_EN */
|
||||
dword |= (1<<17);
|
||||
pci_write_config32(ctrl->d0, 0x7c, dword);
|
||||
|
||||
*/
|
||||
#endif
|
||||
}
|
||||
|
||||
#if DEBUG_RAM_CONFIG
|
||||
dumpnorth();
|
||||
|
|
@ -1863,15 +1833,23 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
int i;
|
||||
uint32_t mchtst;
|
||||
/* 1 & 2 Power up and start clocks */
|
||||
/* arg! the parts are memory mapped! For now, just grab address 0xc0000000 as the base, since I want to use
|
||||
* constants, not variables, for this.
|
||||
/* let the games begin. More undocumented shit, so we'll just set it
|
||||
* as intel sets it
|
||||
*/
|
||||
mchtst = pci_read_config32(ctrl->d0, 0xf4);
|
||||
mchtst |= (1 << 22);
|
||||
pci_write_config32(ctrl->d0, 0xf4, mchtst);
|
||||
|
||||
mchtst = pci_read_config32(ctrl->d0, 0x68);
|
||||
#if DEBUG_RAM_CONFIG
|
||||
print_debug(ram_enable_1);
|
||||
print_debug_hex32(mchtst);
|
||||
dumpnorth();
|
||||
#endif
|
||||
/*
|
||||
mchtst = 0x10f10038;
|
||||
pci_write_config32(ctrl->d0, 0x68, mchtst);
|
||||
* can't find a ram power register ...
|
||||
*/
|
||||
|
||||
#if DEBUG_RAM_CONFIG
|
||||
|
||||
print_debug(ram_enable_2);
|
||||
#endif
|
||||
|
||||
|
|
@ -1882,15 +1860,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
|
||||
/* 3. Apply NOP */
|
||||
#if DEBUG_RAM_CONFIG
|
||||
dump_pci_device(PCI_DEV(0, 0, 0)) ;
|
||||
print_debug(ram_enable_3);
|
||||
#endif
|
||||
RAM_NOP(ctrl);
|
||||
EXTRA_DELAY
|
||||
|
||||
#define DEBUG_RAM_CONFIG 0
|
||||
/* 4 Precharge all */
|
||||
#if DEBUG_RAM_CONFIG
|
||||
print_debug(ram_enable_4);
|
||||
#endif
|
||||
#define DEBUG_RAM_CONFIG 0
|
||||
RAM_PRECHARGE(ctrl);
|
||||
EXTRA_DELAY
|
||||
|
||||
|
|
@ -1975,6 +1955,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
|
||||
//SPECIAL_FINISHUP();
|
||||
dram_finish(ctrl);
|
||||
{ char *c = (char *) 0;
|
||||
*c = 'a';
|
||||
print_debug("Test: ");
|
||||
print_debug_hex8(*c);
|
||||
print_debug("\r\n");
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue