From 4fa8a6f4fefe04eaa1579c03d36abf0fbc9a27f7 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 14 Mar 2017 16:37:55 -0700 Subject: [PATCH] intel/skylake: Fix bug in VR configuration with FSP 2.0 With the move to FSP 2.0 the number of VR types supported was reduced to 4, and the VR_RING type is no longer present. This means all existing boards using FSP 2.0 are incorrectly passing VR configuration into FSP as the values corresponding to "GT Sliced" and "GT Unsliced" have changed. Fix this by updating the skylake SOC VR handling to account for changes in the FSP configuration and no longer provide VR_RING type when using FSP 2.0. BUG=b:36228330 BRANCH=none TEST=manual: build and boot on Eve Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/18818 Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/eve/devicetree.cb | 41 +++++++------------ src/mainboard/google/poppy/devicetree.cb | 41 +++++++------------ .../intel/kblrvp/variants/rvp3/devicetree.cb | 40 +++++++----------- .../intel/kblrvp/variants/rvp7/devicetree.cb | 40 +++++++----------- src/soc/intel/skylake/include/soc/vr_config.h | 16 +++++++- src/soc/intel/skylake/vr_config.c | 2 + 6 files changed, 73 insertions(+), 107 deletions(-) diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 1cef26c388..22b49d7116 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -61,20 +61,20 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 4A | 24A | 24A | 24A | 24A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 4A | 24A | 24A | 24A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -101,19 +101,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 782f075e0e..bdf16e6456 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -65,20 +65,20 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -105,19 +105,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb index c2dde4f526..00b20ba3f7 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb @@ -59,20 +59,20 @@ chip soc/intel/skylake # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled register "SerialIrqConfigSirqEnable" = "0x01" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = 0x50, \ @@ -98,18 +98,6 @@ chip soc/intel/skylake .icc_max = 0x88, \ .voltage_limit = 0x5F0 \ }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0, \ - }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, \ diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb index e79c046b8f..369629263b 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb @@ -65,20 +65,20 @@ chip soc/intel/skylake # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled register "SerialIrqConfigSirqEnable" = "0x01" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = 0x50, \ @@ -104,18 +104,6 @@ chip soc/intel/skylake .icc_max = 0x0, \ .voltage_limit = 0x0 \ }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 0x0, \ - }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, \ diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 1c19b8870e..27d84b2629 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -65,11 +65,12 @@ struct vr_config { #define VR_CFG_AMP(i) ((i) * 4) +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ -enum vr_domain{ +enum vr_domain { VR_SYSTEM_AGENT, VR_IA_CORE, VR_RING, @@ -77,6 +78,19 @@ enum vr_domain{ VR_GT_SLICED, NUM_VR_DOMAINS }; +#else +/* VrConfig Settings for 4 domains + * 0 = System Agent, 1 = IA Core, + * 2 = GT unsliced, 3 = GT sliced + */ +enum vr_domain { + VR_SYSTEM_AGENT, + VR_IA_CORE, + VR_GT_UNSLICED, + VR_GT_SLICED, + NUM_VR_DOMAINS +}; +#endif void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 17ccd7dd93..36c2f1f403 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -44,6 +44,7 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .icc_max = VR_CFG_AMP(34), .voltage_limit = 1520, }, +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) [VR_RING] = { .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -56,6 +57,7 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .icc_max = VR_CFG_AMP(34), .voltage_limit = 1520, }, +#endif [VR_GT_UNSLICED] = { .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20),