1.1.6 adaptions
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
1943d501b4
commit
4fac6cfef8
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@ -23,6 +23,12 @@ uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE=524288
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@ -45,7 +51,7 @@ default HAVE_HARD_RESET=1
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=7
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default IRQ_SLOT_COUNT=9
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##
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## Build code to export an x86 MP table
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@ -58,6 +64,13 @@ default HAVE_MP_TABLE=1
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##
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default HAVE_OPTION_TABLE=1
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##
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
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##
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default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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@ -73,8 +86,8 @@ default CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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#default MAINBOARD_PART_NUMBER="QUARTET"
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#default MAINBOARD_VENDOR="AMD"
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default MAINBOARD_PART_NUMBER="QUARTET"
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default MAINBOARD_VENDOR="AMD"
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###
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### LinuxBIOS layout values
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@ -163,12 +176,12 @@ makerule ./failover.inc
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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depends "$(MAINBOARD)/auto.c option_table.h"
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action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
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end
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##
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@ -176,6 +189,7 @@ end
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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mainboardinit cpu/i386/bist32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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@ -334,4 +348,5 @@ end
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##
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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mainboardinit cpu/i386/bist32_fail.inc
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@ -4,14 +4,16 @@
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <device/pnp.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/smp/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/k8/apic_timer.c"
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@ -20,8 +22,25 @@
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "debug.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#include "superio/NSC/pc87360/pc87360_early_serial.c"
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#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
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static void hard_reset(void)
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{
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set_bios_reset();
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/* enable cf9 */
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pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
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/* reset */
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outb(0x0e, 0x0cf9);
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}
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static void soft_reset(void)
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{
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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}
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#define SIO_BASE 0x2e
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static void memreset_setup(void)
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{
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@ -134,59 +153,6 @@ static void coherent_ht_mainboard(unsigned cpus)
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#include "resourcemap.c" /* quartet does not want the default */
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static void enable_lapic(void)
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{
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msr_t msr;
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msr = rdmsr(0x1b);
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msr.hi &= 0xffffff00;
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msr.lo &= 0x000007ff;
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msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
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wrmsr(0x1b, msr);
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}
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static void stop_this_cpu(void)
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{
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unsigned apicid;
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apicid = apic_read(APIC_ID) >> 24;
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/* Send an APIC INIT to myself */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* Deassert the APIC INIT */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* If I haven't halted spin forever */
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for(;;) {
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hlt();
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}
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}
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#define PC87360_FDC 0x00
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#define PC87360_PP 0x01
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#define PC87360_SP2 0x02
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#define PC87360_SP1 0x03
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#define PC87360_SWC 0x04
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#define PC87360_KBCM 0x05
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#define PC87360_KBCK 0x06
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#define PC87360_GPIO 0x07
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#define PC87360_ACB 0x08
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#define PC87360_FSCM 0x09
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#define PC87360_WDT 0x0A
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static void pc87360_enable_serial(void)
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{
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pnp_set_logical_device(SIO_BASE, PC87360_SP1);
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pnp_set_enable(SIO_BASE, 1);
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pnp_set_iobase0(SIO_BASE, 0x3f8);
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}
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#define RC0 ((1<<1)<<8)
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#define RC1 ((1<<2)<<8)
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#define RC2 ((1<<3)<<8)
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@ -237,23 +203,31 @@ static void main(void)
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.channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
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}
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};
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int needs_reset;
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enable_lapic();
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init_timer();
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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}
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enable_lapic();
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init_timer();
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distinguish_cpu_resets();
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if (!boot_cpu()) {
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// notify_bsp_ap_is_stopped();
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stop_this_cpu();
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}
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pc87360_enable_serial();
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pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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setup_quartet_resource_map();
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setup_coherent_ht_domain();
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enumerate_ht_chain(0);
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distinguish_cpu_resets(0);
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needs_reset = setup_coherent_ht_domain();
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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if (needs_reset) {
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print_info("ht reset -");
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soft_reset();
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}
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#if 0
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print_pci_devices();
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#endif
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@ -270,33 +244,8 @@ static void main(void)
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#if 0
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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#endif
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/* Check all of memory */
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#if 0
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msr_t msr;
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msr = rdmsr(TOP_MEM);
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print_debug("TOP_MEM: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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#endif
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#if 0
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ram_check(0x00000000, msr.lo);
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#endif
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#if 0
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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#if 0
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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#endif
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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/* Check the first 1M */
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ram_check(0x00000000, 0x000100000);
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#endif
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}
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@ -29,6 +29,9 @@ entries
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 1 hw_scrubber
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396 1 e 1 interleave_chip_selects
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397 2 e 8 max_mem_clock
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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@ -36,7 +39,14 @@ entries
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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1008 16 h 0 check_sum
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440 4 e 9 slow_cpu
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444 1 e 1 nmi
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 reserved_memory
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enumerations
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@ -66,9 +76,21 @@ enumerations
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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8 0 200Mhz
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8 1 166Mhz
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8 2 133Mhz
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8 3 100Mhz
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9 0 off
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9 1 87.5%
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9 2 75.0%
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9 3 62.5%
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9 4 50.0%
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9 5 37.5%
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9 6 25.0%
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9 7 12.5%
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checksums
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checksum 392 1007 1008
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checksum 392 983 984
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@ -14,7 +14,7 @@ static void main(void)
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{
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain(0);
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enumerate_ht_chain();
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/* Setup the 8111 */
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amd8111_enable_rom();
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