soc/intel/common: add processor power limits control support
Add processor power limits control support under common code. BRANCH=None BUG=None TEST=Built and checked this entry on Volteer system, cat /sys/class/powercap/intel-rapl/intel-rapl\:0/* Change-Id: I41fd95949aa2b02828aa2d13d29b962cb579904a Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet R Pawnikar
Patrick Georgi
parent
5f52c0e91f
commit
4fafd41209
4 changed files with 245 additions and 0 deletions
41
src/soc/intel/common/block/include/intelblocks/power_limit.h
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41
src/soc/intel/common/block/include/intelblocks/power_limit.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_
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#define _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_
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#define MCH_PKG_POWER_LIMIT_LO 0x59a0
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#define MCH_PKG_POWER_LIMIT_HI 0x59a4
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#define MCH_DDR_POWER_LIMIT_LO 0x58e0
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#define MCH_DDR_POWER_LIMIT_HI 0x58e4
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#define MSR_VR_CURRENT_CONFIG 0x601
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#define MSR_PL3_CONTROL 0x615
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#define MSR_PLATFORM_POWER_LIMIT 0x65c
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/* Default power limit value in secs */
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#define MOBILE_SKU_PL1_TIME_SEC 28
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struct soc_power_limits_config {
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/* PL1 Override value in Watts */
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uint16_t tdp_pl1_override;
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/* PL2 Override value in Watts */
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uint16_t tdp_pl2_override;
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/* SysPL2 Value in Watts */
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uint16_t tdp_psyspl2;
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/* SysPL3 Value in Watts */
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uint16_t tdp_psyspl3;
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/* SysPL3 window size */
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uint32_t tdp_psyspl3_time;
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/* SysPL3 duty cycle */
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uint32_t tdp_psyspl3_dutycycle;
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/* PL4 Value in Watts */
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uint16_t tdp_pl4;
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/* Estimated maximum platform power in Watts */
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uint16_t psys_pmax;
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};
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/* Configure power limits for turbo mode */
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void set_power_limits(u8 power_limit_1_time,
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struct soc_power_limits_config *config);
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#endif /* _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ */
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5
src/soc/intel/common/block/power_limit/Kconfig
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src/soc/intel/common/block/power_limit/Kconfig
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config SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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bool
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default n
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help
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This option allows to configure processor power limit values.
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1
src/soc/intel/common/block/power_limit/Makefile.inc
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1
src/soc/intel/common/block/power_limit/Makefile.inc
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@ -0,0 +1 @@
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT) += power_limit.c
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198
src/soc/intel/common/block/power_limit/power_limit.c
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198
src/soc/intel/common/block/power_limit/power_limit.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/power_limit.h>
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#include <soc/msr.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
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static const u8 power_limit_time_sec_to_msr[] = {
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[0] = 0x00,
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[1] = 0x0a,
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[2] = 0x0b,
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[3] = 0x4b,
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[4] = 0x0c,
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[5] = 0x2c,
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[6] = 0x4c,
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[7] = 0x6c,
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[8] = 0x0d,
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[10] = 0x2d,
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[12] = 0x4d,
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[14] = 0x6d,
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[16] = 0x0e,
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[20] = 0x2e,
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[24] = 0x4e,
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[28] = 0x6e,
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[32] = 0x0f,
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[40] = 0x2f,
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[48] = 0x4f,
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[56] = 0x6f,
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[64] = 0x10,
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[80] = 0x30,
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[96] = 0x50,
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[112] = 0x70,
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[128] = 0x11,
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};
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/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
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static const u8 power_limit_time_msr_to_sec[] = {
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[0x00] = 0,
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[0x0a] = 1,
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[0x0b] = 2,
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[0x4b] = 3,
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[0x0c] = 4,
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[0x2c] = 5,
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[0x4c] = 6,
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[0x6c] = 7,
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[0x0d] = 8,
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[0x2d] = 10,
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[0x4d] = 12,
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[0x6d] = 14,
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[0x0e] = 16,
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[0x2e] = 20,
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[0x4e] = 24,
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[0x6e] = 28,
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[0x0f] = 32,
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[0x2f] = 40,
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[0x4f] = 48,
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[0x6f] = 56,
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[0x10] = 64,
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[0x30] = 80,
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[0x50] = 96,
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[0x70] = 112,
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[0x11] = 128,
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};
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/*
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* Configure processor power limits if possible
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* This must be done AFTER set of BIOS_RESET_CPL
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*/
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void set_power_limits(u8 power_limit_1_time,
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struct soc_power_limits_config *conf)
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{
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msr_t msr = rdmsr(MSR_PLATFORM_INFO);
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msr_t limit;
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unsigned int power_unit;
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unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
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u8 power_limit_1_val;
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if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
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power_limit_1_time =
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ARRAY_SIZE(power_limit_time_sec_to_msr) - 1;
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if (!(msr.lo & PLATFORM_INFO_SET_TDP))
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return;
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/* Get units */
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msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
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power_unit = 1 << (msr.lo & 0xf);
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/* Get power defaults for this SKU */
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msr = rdmsr(MSR_PKG_POWER_SKU);
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tdp = msr.lo & 0x7fff;
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min_power = (msr.lo >> 16) & 0x7fff;
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max_power = msr.hi & 0x7fff;
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max_time = (msr.hi >> 16) & 0x7f;
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printk(BIOS_INFO, "CPU TDP = %u Watts\n", tdp / power_unit);
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if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
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power_limit_1_time = power_limit_time_msr_to_sec[max_time];
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if (min_power > 0 && tdp < min_power)
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tdp = min_power;
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if (max_power > 0 && tdp > max_power)
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tdp = max_power;
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power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
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/* Set long term power limit to TDP */
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limit.lo = 0;
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tdp_pl1 = ((conf->tdp_pl1_override == 0) ?
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tdp : (conf->tdp_pl1_override * power_unit));
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printk(BIOS_INFO, "CPU PL1 = %u Watts\n", tdp_pl1 / power_unit);
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limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK);
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/* Set PL1 Pkg Power clamp bit */
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limit.lo |= PKG_POWER_LIMIT_CLAMP;
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limit.lo |= PKG_POWER_LIMIT_EN;
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limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
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PKG_POWER_LIMIT_TIME_SHIFT;
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/* Set short term power limit to 1.25 * TDP if no config given */
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limit.hi = 0;
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tdp_pl2 = (conf->tdp_pl2_override == 0) ?
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(tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit);
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printk(BIOS_INFO, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit);
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limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK;
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limit.hi |= PKG_POWER_LIMIT_CLAMP;
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limit.hi |= PKG_POWER_LIMIT_EN;
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/* Power limit 2 time is only programmable on server SKU */
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wrmsr(MSR_PKG_POWER_LIMIT, limit);
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/* Set PL2 power limit values in MCHBAR and disable PL1 */
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MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN));
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MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
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/* Set PsysPl2 */
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if (conf->tdp_psyspl2) {
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limit = rdmsr(MSR_PLATFORM_POWER_LIMIT);
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limit.hi = 0;
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printk(BIOS_INFO, "CPU PsysPL2 = %u Watts\n",
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conf->tdp_psyspl2);
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limit.hi |= (conf->tdp_psyspl2 * power_unit) &
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PKG_POWER_LIMIT_MASK;
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limit.hi |= PKG_POWER_LIMIT_CLAMP;
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limit.hi |= PKG_POWER_LIMIT_EN;
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wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
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}
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/* Set PsysPl3 */
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if (conf->tdp_psyspl3) {
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limit = rdmsr(MSR_PL3_CONTROL);
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limit.lo = 0;
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printk(BIOS_INFO, "CPU PsysPL3 = %u Watts\n",
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conf->tdp_psyspl3);
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limit.lo |= (conf->tdp_psyspl3 * power_unit) &
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PKG_POWER_LIMIT_MASK;
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/* Enable PsysPl3 */
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limit.lo |= PKG_POWER_LIMIT_EN;
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/* set PsysPl3 time window */
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limit.lo |= (conf->tdp_psyspl3_time &
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PKG_POWER_LIMIT_TIME_MASK) <<
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PKG_POWER_LIMIT_TIME_SHIFT;
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/* set PsysPl3 duty cycle */
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limit.lo |= (conf->tdp_psyspl3_dutycycle &
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PKG_POWER_LIMIT_DUTYCYCLE_MASK) <<
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PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;
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wrmsr(MSR_PL3_CONTROL, limit);
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}
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/* Set Pl4 */
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if (conf->tdp_pl4) {
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limit = rdmsr(MSR_VR_CURRENT_CONFIG);
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limit.lo = 0;
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printk(BIOS_INFO, "CPU PL4 = %u Watts\n", conf->tdp_pl4);
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limit.lo |= (conf->tdp_pl4 * power_unit) &
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PKG_POWER_LIMIT_MASK;
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wrmsr(MSR_VR_CURRENT_CONFIG, limit);
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}
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/* Set DDR RAPL power limit by copying from MMIO to MSR */
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msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
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msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
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wrmsr(MSR_DDR_RAPL_LIMIT, msr);
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/* Use nominal TDP values for CPUs with configurable TDP */
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if (cpu_config_tdp_levels()) {
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limit.hi = 0;
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limit.lo = cpu_get_tdp_nominal_ratio();
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wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
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}
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}
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