mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-05-31 19:44:46 +02:00
parent c4eb45fa85
commit 4fbab545b2
7 changed files with 33 additions and 33 deletions

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@ -140,11 +140,11 @@ chip soc/amd/picasso
device domain 0 on
subsystemid 0x1022 0x1510 inherit
device pci 0.2 on end # IOMMU
device pci 1.1 on end # GPP Bridge 0
device pci 1.2 on end # GPP Bridge 1
device pci 1.5 on end # NVMe
device pci 8.1 on # Bridge to Bus A
device ref iommu on end
device ref gpp_bridge_0 on end
device ref gpp_bridge_1 on end
device ref gpp_bridge_4 on end # NVMe
device ref internal_bridge_a on
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocessor
@ -154,12 +154,12 @@ chip soc/amd/picasso
device pci 0.6 on end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
device pci 8.2 on # Bridge to Bus B
device ref internal_bridge_b on
device pci 0.0 off end # AHCI
device pci 0.1 off end # integrated Ethernet MAC
device pci 0.2 off end # integrated Ethernet MAC
end
device pci 14.3 on # D14F3 bridge
device ref lpc_bridge on
chip superio/smsc/sio1036 # optional debug card
end
end

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@ -140,9 +140,9 @@ chip soc/amd/picasso
device domain 0 on
subsystemid 0x1022 0x1510 inherit
device pci 0.2 on end # IOMMU
device pci 1.1 on end # Bridge to PCIe Ethernet chip
device pci 8.1 on # Bridge to Bus A
device ref iommu on end
device ref gpp_bridge_0 on end # Bridge to PCIe Ethernet chip
device ref internal_bridge_a on
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocessor
@ -152,12 +152,12 @@ chip soc/amd/picasso
device pci 0.6 on end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
device pci 8.2 on # Bridge to Bus B
device ref internal_bridge_b on
device pci 0.0 off end # AHCI
device pci 0.1 off end # integrated Ethernet MAC
device pci 0.2 off end # integrated Ethernet MAC
end
device pci 14.3 on # D14F3 bridge
device ref lpc_bridge on
chip superio/smsc/sio1036 # optional debug card
end
end

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@ -140,9 +140,9 @@ chip soc/amd/picasso
device domain 0 on
subsystemid 0x1022 0x1510 inherit
device pci 0.2 on end # IOMMU
device pci 1.3 on end # Bridge to PCIe Ethernet chip
device pci 8.1 on # Bridge to Bus A
device ref iommu on end
device ref gpp_bridge_2 on end # Bridge to PCIe Ethernet chip
device ref internal_bridge_a on
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocessor
@ -152,12 +152,12 @@ chip soc/amd/picasso
device pci 0.6 on end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
device pci 8.2 on # Bridge to Bus B
device ref internal_bridge_b on
device pci 0.0 on end # AHCI
device pci 0.1 off end # integrated Ethernet MAC
device pci 0.2 off end # integrated Ethernet MAC
end
device pci 14.3 on # D14F3 bridge
device ref lpc_bridge on
chip superio/smsc/sio1036 # optional debug card
end
end

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@ -255,15 +255,15 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
device pci 0.2 on end # IOMMU
device pci 1.2 on # GPP Bridge 1 - Wifi
device ref iommu on end
device ref gpp_bridge_1 on # Wifi
chip drivers/wifi/generic
register "wake" = "GEVENT_8"
device pci 00.0 on end
end
end
device pci 1.3 on end # GPP Bridge 2 - SD
device pci 8.1 on # Internal GPP Bridge 0 to Bus A
device ref gpp_bridge_2 on end # SD
device ref internal_bridge_a on
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocessor
@ -353,7 +353,7 @@ chip soc/amd/picasso
device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
device pci 14.3 on # - D14F3 bridge
device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 on
chip ec/google/chromeec/i2c_tunnel

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@ -248,16 +248,16 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
device pci 0.2 on end # IOMMU
device pci 1.2 on # GPP Bridge 1 - Wifi
device ref iommu on end
device ref gpp_bridge_1 on # Wifi
chip drivers/wifi/generic
register "wake" = "GEVENT_8"
device pci 00.0 on end
end
end
device pci 1.3 on end # GPP Bridge 2 - SD
device pci 1.7 on end # GPP Bridge 6 - NVME
device pci 8.1 on # Internal GPP Bridge 0 to Bus A
device ref gpp_bridge_2 on end # SD
device ref gpp_bridge_6 on end # NVME
device ref internal_bridge_a on
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocessor
@ -374,7 +374,7 @@ chip soc/amd/picasso
device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
device pci 14.3 on # - D14F3 bridge
device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 on
chip ec/google/chromeec/i2c_tunnel

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@ -152,13 +152,13 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
device pci 1.3 on
device ref gpp_bridge_2 on
chip drivers/generic/bayhub_lv2
register "enable_power_saving" = "1"
device pci 00.0 on end
end
end # GPP Bridge 2 - SD
device pci 8.1 on
end # SD
device ref internal_bridge_a on
device pci 0.5 on
chip drivers/amd/i2s_machine_dev
register "hid" = ""AMDI1015""
@ -200,7 +200,7 @@ chip soc/amd/picasso
end
end # Audio
end
device pci 14.3 on # - D14F3 bridge
device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 on
chip ec/google/chromeec/i2c_tunnel

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@ -37,7 +37,7 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
device pci 1.7 on end # GPP Bridge 6 - NVME
device ref gpp_bridge_6 on end # NVME
end # domain
device mmio 0xfedc4000 on end