soc/amd/stoneyridge: Replace public magic numbers
Some "magic" numbers became public available registers/bits after the code was originally written. Find all magic numbers, and if available in a public BKDG than replace them with literals. BUG=b:117648026 TEST=Build and boot grunt. Change-Id: I96ac59fd92c4a5e27c3836f77bf6633e9b0c4990 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -31,6 +31,7 @@
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#include <soc/acpi.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include <soc/northbridge.h>
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#include <soc/nvs.h>
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#include <soc/gpio.h>
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@ -237,11 +238,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
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void generate_cpu_entries(struct device *device)
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{
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int cores, cpu;
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struct device *cdb_dev;
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/* Stoney Ridge is single node, just report # of cores */
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cdb_dev = dev_find_slot(0, NB_DEVFN);
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cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1;
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cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
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cores++; /* number of cores is CmpCap+1 */
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printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
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@ -62,9 +62,15 @@
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# define MMIO_RE (1 << 0)
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#define D18F1_MMIO_LIMIT0_LO 0x84
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# define MMIO_NP (1 << 7)
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#define D18F1_IO_BASE0_LO 0xc0
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#define D18F1_IO_BASE1_LO 0xc8
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#define D18F1_IO_BASE2_LO 0xd0
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#define D18F1_IO_BASE3_LO 0xd8
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#define D18F1_MMIO_BASE7_LO 0xb8
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#define D18F1_MMIO_BASELIM0_HI 0x180
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#define D18F1_MMIO_BASE8_LO 0x1a0
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#define D18F1_MMIO_LIMIT8_LO 0x1a4
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#define D18F1_MMIO_BASE11_LO 0x1b8
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#define D18F1_MMIO_BASELIM8_HI 0x1c0
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#define NB_MMIO_BASE_LO(reg) ((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \
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? D18F1_MMIO_BASE0_LO \
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@ -89,6 +95,10 @@
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#define D18F1_VGAEN 0xf4
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# define VGA_ADDR_ENABLE (1 << 0)
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/* D18F5 */
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#define NB_CAPABILITIES2 0x84
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#define CMP_CAP_MASK 0xff
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enum {
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/* SMM handler area. */
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SMM_SUBREGION_HANDLER,
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@ -304,6 +304,7 @@
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#define LPC_WIDEIO2_GENERIC_PORT 0x90
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#define SPIROM_BASE_ADDRESS_REGISTER 0xa0
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#define SPI_BASE_RESERVED (BIT(4) | BIT(5))
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#define ROUTE_TPM_2_SPI BIT(3)
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#define SPI_ABORT_ENABLE BIT(2)
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#define SPI_ROM_ENABLE BIT(1)
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@ -414,8 +414,8 @@ static uintptr_t sb_spibase(void)
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/* Make sure the base address is predictable */
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base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);
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enables = base & 0xf;
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base &= ~0x3f;
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enables = base & SPI_PRESERVE_BITS;
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base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED);
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if (!base) {
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base = SPI_BASE_ADDRESS;
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