soc/mediatek/mt8186: Modify internal capid to 0xE0
The mainboard may not be able to disable the internal cap, so we want to set 0xe0 for all boards to minimize the internal cap. And a mainboard implementation may choose XTAL with higher cload if the frequency requirement is met, and the total capacitance can be tuned externally for different boards. BUG=b:218439447 TEST=set capid to 0xe0. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62563 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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#include <soc/pmic_wrap.h>
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#include <timer.h>
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#define MT8186_RTC_DXCO_CAPID 0xC0
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#define MT8186_RTC_DXCO_CAPID 0xE0
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/* Initialize RTC setting of using DCXO clock */
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static bool rtc_enable_dcxo(void)
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