GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/mediatek/mt8186: Modify internal capid to 0xE0 

The mainboard may not be able to disable the internal cap, so we want
to set 0xe0 for all boards to minimize the internal cap. And a
mainboard implementation may choose XTAL with higher cload if the
frequency requirement is met, and the total capacitance can be tuned
externally for different boards.

BUG=b:218439447
TEST=set capid to 0xe0.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62563
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Rex-BC Chen 2022-03-03 19:16:04 +08:00 committed by Felix Held
parent 6277077d88
commit 4fd80b286b
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/mediatek/mt8186/rtc.c
View File

@ -13,7 +13,7 @@
#include <soc/pmic_wrap.h> #include <soc/pmic_wrap.h>
#include <timer.h> #include <timer.h>
#define MT8186_RTC_DXCO_CAPID 0xC0 #define MT8186_RTC_DXCO_CAPID 0xE0
/* Initialize RTC setting of using DCXO clock */ /* Initialize RTC setting of using DCXO clock */
static bool rtc_enable_dcxo(void) static bool rtc_enable_dcxo(void)