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soc/amd/picasso/include: unify include guards 

Change-Id: I980cdd03d4283cd4bd9db8bd90fde9a43bebc1e5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Felix Held 2020-11-13 23:58:41 +01:00
parent aa003fecfd
commit 4feef09c65
21 changed files with 63 additions and 63 deletions
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6
src/soc/amd/picasso/include/soc/acp.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PI_PICASSO_ACP_H__
#define __PI_PICASSO_ACP_H__
#ifndef AMD_PICASSO_ACP_H
#define AMD_PICASSO_ACP_H
/* Bus A D0F5 - Audio Processor */
#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */
@ -11,4 +11,4 @@
#define ACP_PME_EN 0x1418
#define PME_EN_MASK (1 << 0)
#endif /* __PI_PICASSO_ACP_H__ */
#endif /* AMD_PICASSO_ACP_H */

6
src/soc/amd/picasso/include/soc/acpi.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __SOC_PICASSO_ACPI_H__
#define __SOC_PICASSO_ACPI_H__
#ifndef AMD_PICASSO_ACPI_H
#define AMD_PICASSO_ACPI_H
#include <acpi/acpi.h>
#include <amdblocks/acpi.h>
@ -21,4 +21,4 @@ struct chipset_state {
struct gpio_wake_state gpio_state;
};
#endif /* __SOC_PICASSO_ACPI_H__ */
#endif /* AMD_PICASSO_ACPI_H */

6
src/soc/amd/picasso/include/soc/amd_pci_int_defs.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __AMD_PCI_INT_DEFS_H__
#define __AMD_PCI_INT_DEFS_H__
#ifndef AMD_PICASSO_AMD_PCI_INT_DEFS_H
#define AMD_PICASSO_AMD_PCI_INT_DEFS_H
/*
* PIRQ and device routing - these define the index into the
@ -61,4 +61,4 @@
#define PIRQ_UART3 0x79 /* UART3 */
/* 0x7a-0x7f reserved */
#endif /* __AMD_PCI_INT_DEFS_H__ */
#endif /* AMD_PICASSO_AMD_PCI_INT_DEFS_H */

6
src/soc/amd/picasso/include/soc/cpu.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PICASSO_CPU_H__
#define __PICASSO_CPU_H__
#ifndef AMD_PICASSO_CPU_H
#define AMD_PICASSO_CPU_H
int get_cpu_count(void);
void check_mca(void);
@ -19,4 +19,4 @@ void check_mca(void);
#define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */
#define RAVEN2_VBIOS_REV 0xc4
#endif /* __PICASSO_CPU_H__ */
#endif /* AMD_PICASSO_CPU_H */

6
src/soc/amd/picasso/include/soc/data_fabric.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_PICASSO_DATAFABRIC_H__
#define __SOC_PICASSO_DATAFABRIC_H__
#ifndef AMD_PICASSO_DATA_FABRIC_H
#define AMD_PICASSO_DATA_FABRIC_H
#include <types.h>
@ -26,4 +26,4 @@
void data_fabric_set_mmio_np(void);
#endif /* __SOC_PICASSO_DATAFABRIC_H__ */
#endif /* AMD_PICASSO_DATA_FABRIC_H */

6
src/soc/amd/picasso/include/soc/gpio.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PICASSO_GPIO_H__
#define __PICASSO_GPIO_H__
#ifndef AMD_PICASSO_GPIO_H
#define AMD_PICASSO_GPIO_H
#define GPIO_DEVICE_NAME "AMD0030"
#define GPIO_DEVICE_DESC "GPIO Controller"
@ -297,4 +297,4 @@
#define GPIO_2_EVENT GEVENT_8
#endif /* __ACPI__ */
#endif /* __PICASSO_GPIO_H__ */
#endif /* AMD_PICASSO_GPIO_H */

6
src/soc/amd/picasso/include/soc/i2c.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PICASSO_I2C_H__
#define __PICASSO_I2C_H__
#ifndef AMD_PICASSO_I2C_H
#define AMD_PICASSO_I2C_H
#include <types.h>
#include <soc/gpio.h>
@ -26,4 +26,4 @@ void sb_reset_i2c_slaves(void);
/* Sets the base address for the specific I2C bus. */
void i2c_set_bar(unsigned int bus, uintptr_t bar);
#endif /* __PICASSO_I2C_H__ */
#endif /* AMD_PICASSO_I2C_H */

6
src/soc/amd/picasso/include/soc/iomap.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_PICASSO_IOMAP_H__
#define __SOC_PICASSO_IOMAP_H__
#ifndef AMD_PICASSO_IOMAP_H
#define AMD_PICASSO_IOMAP_H
/* MMIO Ranges */
/* IO_APIC_ADDR defined in arch/x86 0xfec00000 */
@ -90,4 +90,4 @@
#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */
#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
#endif /* __SOC_PICASSO_IOMAP_H__ */
#endif /* AMD_PICASSO_IOMAP_H */

6
src/soc/amd/picasso/include/soc/memmap.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __SOC_AMD_PICASSO_MEMMAP_H__
#define __SOC_AMD_PICASSO_MEMMAP_H__
#ifndef AMD_PICASSO_MEMMAP_H
#define AMD_PICASSO_MEMMAP_H
#include <stdint.h>
#include <symbols.h>
@ -16,4 +16,4 @@ struct memmap_early_dram {
void memmap_stash_early_dram_usage(void);
const struct memmap_early_dram *memmap_get_early_dram_usage(void);
#endif /* __SOC_AMD_PICASSO_MEMMAP_H__ */
#endif /* AMD_PICASSO_MEMMAP_H */

6
src/soc/amd/picasso/include/soc/mrc_cache.h
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@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __PICASSO_MRC_CACHE_H__
#define __PICASSO_MRC_CACHE_H__
#ifndef AMD_PICASSO_MRC_CACHE_H
#define AMD_PICASSO_MRC_CACHE_H
void *soc_fill_mrc_cache(void);
void soc_update_mrc_cache(void);
#endif /* __PICASSO_MRC_CACHE_H__ */
#endif /* AMD_PICASSO_MRC_CACHE_H */

6
src/soc/amd/picasso/include/soc/msr.h
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@ -4,8 +4,8 @@
* The definitions come from the device's PPR.
*/
#ifndef SOC_AMD_PICASSO_MSR_H
#define SOC_AMD_PICASSO_MSR_H
#ifndef AMD_PICASSO_MSR_H
#define AMD_PICASSO_MSR_H
/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
#define PSTATE_DEF_HI_ENABLE_SHIFT 31
@ -25,4 +25,4 @@
#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
#define PSTATE_DEF_LO_CORE_FREQ_BASE 25
#endif /* SOC_AMD_PICASSO_MSR_H */
#endif /* AMD_PICASSO_MSR_H */

6
src/soc/amd/picasso/include/soc/nvs.h
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@ -6,8 +6,8 @@
*
*/
#ifndef __SOC_PICASSO_NVS_H__
#define __SOC_PICASSO_NVS_H__
#ifndef AMD_PICASSO_NVS_H
#define AMD_PICASSO_NVS_H
#include <commonlib/helpers.h>
#include <stdint.h>
@ -33,4 +33,4 @@ struct __packed global_nvs {
check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* __SOC_PICASSO_NVS_H__ */
#endif /* AMD_PICASSO_NVS_H */

6
src/soc/amd/picasso/include/soc/pci_devs.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PI_PICASSO_PCI_DEVS_H__
#define __PI_PICASSO_PCI_DEVS_H__
#ifndef AMD_PICASSO_PCI_DEVS_H
#define AMD_PICASSO_PCI_DEVS_H
#include <device/pci_def.h>
#include <amdblocks/pci_devs.h>
@ -118,4 +118,4 @@
#define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC)
#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC)
#endif /* __PI_PICASSO_PCI_DEVS_H__ */
#endif /* AMD_PICASSO_PCI_DEVS_H */

6
src/soc/amd/picasso/include/soc/platform_descriptors.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PICASSO_PLATFORM_DESCRIPTORS_H__
#define __PICASSO_PLATFORM_DESCRIPTORS_H__
#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H
#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H
#include <types.h>
#include <platform_descriptors.h>
@ -27,4 +27,4 @@ void mainboard_get_dxio_ddi_descriptors(
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num);
#endif /* __PICASSO_PLATFORM_DESCRIPTORS_H__ */
#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */

6
src/soc/amd/picasso/include/soc/psp_transfer.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef PSP_VERSTAGE_PSP_TRANSFER_H
#define PSP_VERSTAGE_PSP_TRANSFER_H
#ifndef AMD_PICASSO_PSP_TRANSFER_H
#define AMD_PICASSO_PSP_TRANSFER_H
# if (CONFIG_CMOS_RECOVERY_BYTE != 0)
# define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE
@ -49,4 +49,4 @@ void show_psp_transfer_info(void);
#endif
#endif /* PSP_VERSTAGE_PSP_TRANSFER_H */
#endif /* AMD_PICASSO_PSP_TRANSFER_H */

6
src/soc/amd/picasso/include/soc/reset.h
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@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PI_PICASSO_RESET_H__
#define __PI_PICASSO_RESET_H__
#ifndef AMD_PICASSO_RESET_H
#define AMD_PICASSO_RESET_H
void set_warm_reset_flag(void);
int is_warm_reset(void);
#endif /* __PI_PICASSO_RESET_H__ */
#endif /* AMD_PICASSO_RESET_H */

6
src/soc/amd/picasso/include/soc/smi.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__
#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__
#ifndef AMD_PICASSO_SMI_H
#define AMD_PICASSO_SMI_H
#include <types.h>
@ -221,4 +221,4 @@ void disable_gevent_smi(uint8_t gevent);
void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
void soc_route_sci(uint8_t event);
#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */
#endif /* AMD_PICASSO_SMI_H */

6
src/soc/amd/picasso/include/soc/smu.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PICASSO_SMU_H__
#define __PICASSO_SMU_H__
#ifndef AMD_PICASSO_SMU_H
#define AMD_PICASSO_SMU_H
/*
* SMU mailbox register offsets in indirect address space accessed by an index/data pair in
@ -23,4 +23,4 @@ enum smu_message_id {
*/
void smu_sx_entry(void);
#endif /* __PICASSO_SMU_H__ */
#endif /* AMD_PICASSO_SMU_H */

6
src/soc/amd/picasso/include/soc/soc_util.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PICASSO_SOC_UTIL_H__
#define __PICASSO_SOC_UTIL_H__
#ifndef AMD_PICASSO_SOC_UTIL_H
#define AMD_PICASSO_SOC_UTIL_H
#include <types.h>
@ -39,4 +39,4 @@ bool soc_is_reduced_io_sku(void);
/* function to determine the iGPU type */
bool soc_is_raven2(void);
#endif /* __PICASSO_SOC_UTIL_H__ */
#endif /* AMD_PICASSO_SOC_UTIL_H */

6
src/soc/amd/picasso/include/soc/southbridge.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PICASSO_SB_H__
#define __PICASSO_SB_H__
#ifndef AMD_PICASSO_SOUTHBRIDGE_H
#define AMD_PICASSO_SOUTHBRIDGE_H
#include <types.h>
#include <device/device.h>
@ -294,4 +294,4 @@ void i2c_soc_init(void);
/* Allow the board to change the default I2C pad configuration */
void mainboard_i2c_override(int bus, uint32_t *pad_settings);
#endif /* __PICASSO_SB_H__ */
#endif /* AMD_PICASSO_SOUTHBRIDGE_H */

6
src/soc/amd/picasso/include/soc/uart.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PICASSO_UART_H__
#define __PICASSO_UART_H__
#ifndef AMD_PICASSO_UART_H
#define AMD_PICASSO_UART_H
#include <types.h>
@ -10,4 +10,4 @@ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART *
uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */
#endif /* __PICASSO_UART_H__ */
#endif /* AMD_PICASSO_UART_H */