broadwell: Apply pcie updates from 2.1.0 ref code
some clock gating and pcie settings are missed in original code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214568 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 57e42c781d435092a08238461f0605dbf092e576) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia62a50f28a411bbd2ba51b94de17ca70051ea093 Reviewed-on: http://review.coreboot.org/8967 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -31,6 +31,7 @@
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#include <broadwell/pci_devs.h>
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#include <broadwell/pci_devs.h>
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#include <broadwell/rcba.h>
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#include <broadwell/rcba.h>
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#include <chip.h>
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#include <chip.h>
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#include <broadwell/cpu.h>
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static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
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static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
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static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);
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static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);
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@ -107,6 +108,7 @@ static void root_port_init_config(device_t dev)
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rpc.new_rpfn = rpc.orig_rpfn;
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rpc.new_rpfn = rpc.orig_rpfn;
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rpc.num_ports = NUM_ROOT_PORTS;
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rpc.num_ports = NUM_ROOT_PORTS;
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rpc.gbe_port = -1;
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rpc.gbe_port = -1;
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pcie_update_cfg8(dev, 0xf5, 0xa, 0x5);
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rpc.pin_ownership = pci_read_config32(dev, 0x410);
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rpc.pin_ownership = pci_read_config32(dev, 0x410);
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root_port_config_update_gbe_port();
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root_port_config_update_gbe_port();
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@ -176,6 +178,7 @@ static void pcie_enable_clock_gating(void)
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{
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{
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int i;
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int i;
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int enabled_ports = 0;
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int enabled_ports = 0;
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int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
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for (i = 0; i < rpc.num_ports; i++) {
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for (i = 0; i < rpc.num_ports; i++) {
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device_t dev;
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device_t dev;
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@ -216,9 +219,13 @@ static void pcie_enable_clock_gating(void)
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pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2));
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pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2));
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/* Update PECR1 register. */
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/* Update PECR1 register. */
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pcie_update_cfg8(dev, 0xe8, ~0, 1);
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pcie_update_cfg8(dev, 0xe8, ~0, 3);
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pcie_update_cfg8(dev, 0x324, ~(1 << 5), (1 < 5));
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if (is_broadwell) {
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pcie_update_cfg(dev, 0x324, ~((1 << 5) | (1 << 14)),
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((1 << 5) | (1 << 14)));
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} else {
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pcie_update_cfg(dev, 0x324, ~(1 << 5), (1 << 5));
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}
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/* Per-Port CLKREQ# handling. */
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/* Per-Port CLKREQ# handling. */
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if (gpio_is_native(18 + rp - 1))
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if (gpio_is_native(18 + rp - 1))
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pcie_update_cfg(dev, 0x420, ~0, (3 << 29));
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pcie_update_cfg(dev, 0x420, ~0, (3 << 29));
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@ -455,9 +462,6 @@ static void pch_pcie_early(struct device *dev)
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/* Set unique clock exit latency in MPC register. */
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/* Set unique clock exit latency in MPC register. */
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pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
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pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
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/* Set L1 exit latency in LCAP register. */
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pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
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switch (rp) {
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switch (rp) {
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case 1:
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case 1:
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pcie_add_0x0202000_iobp(0xe9002440);
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pcie_add_0x0202000_iobp(0xe9002440);
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@ -515,7 +519,7 @@ static void pch_pcie_early(struct device *dev)
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/* Set Invalid Receive Range Check Enable in MPC register. */
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/* Set Invalid Receive Range Check Enable in MPC register. */
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pcie_update_cfg(dev, 0xd8, ~0, (1 << 25));
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pcie_update_cfg(dev, 0xd8, ~0, (1 << 25));
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pcie_update_cfg8(dev, 0xf5, 0x3f, 0);
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pcie_update_cfg8(dev, 0xf5, 0x0f, 0);
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if (rp == 1 || rp == 5 || rp == 6)
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if (rp == 1 || rp == 5 || rp == 6)
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pcie_update_cfg8(dev, 0xf7, ~0xc, 0);
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pcie_update_cfg8(dev, 0xf7, ~0xc, 0);
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