soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot

Do it in coreboot code instead of letting FSP do it.

Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/skylake/chip.c

@@ -391,17 +391,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Set TccActivationOffset */
 	tconfig->TccActivationOffset = config->tcc_offset;
 
+	/* Already handled in coreboot code, so tell FSP to ignore UPDs */
+	params->PchIoApicBdfValid = 0;
+
 	/* Enable VT-d and X2APIC */
 	if (!config->ignore_vtd && soc_is_vtd_capable()) {
 		params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
 		params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS;
 		params->X2ApicOptOut = 0;
 		tconfig->VtdDisable = 0;
-
-		params->PchIoApicBdfValid = 1;
-		params->PchIoApicBusNumber = V_P2SB_IBDF_BUS;
-		params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV;
-		params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN;
 	}
 
 	dev = pcidev_path_on_root(SA_DEVFN_IGD);

src/soc/intel/skylake/include/soc/systemagent.h

@@ -66,9 +66,11 @@ static const struct sa_mmio_descriptor soc_vtvc0_mmio_descriptor = {
 #define V_P2SB_IBDF_BUS	250
 #define V_P2SB_IBDF_DEV	31
 #define V_P2SB_IBDF_FUN	0
+#define V_DEFAULT_IBDF	((V_P2SB_IBDF_BUS << 8) | PCI_DEVFN(V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN))
 
 #define V_P2SB_HBDF_BUS	250
 #define V_P2SB_HBDF_DEV	15
 #define V_P2SB_HBDF_FUN	0
+#define V_DEFAULT_HBDF	((V_P2SB_HBDF_BUS << 8) | PCI_DEVFN(V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN))
 
 #endif

src/soc/intel/skylake/romstage/romstage.c

@@ -248,12 +248,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 
 	cpu_flex_override(m_cfg);
 
-	if (!config->ignore_vtd) {
-		m_cfg->PchHpetBdfValid = 1;
-		m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS;
-		m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV;
-		m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN;
-	}
+	/* HPET BDF already handled in coreboot code, so tell FSP to ignore UPDs */
+	m_cfg->PchHpetBdfValid = 0;
+
 	m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING);
 }
 

src/soc/intel/skylake/romstage/systemagent.c

@@ -19,6 +19,7 @@
 #include <device/pci_ops.h>
 #include <intelblocks/systemagent.h>
 #include <soc/iomap.h>
+#include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/systemagent.h>
@@ -38,6 +39,10 @@ static void systemagent_vtd_init(void)
 	if (!vtd_capable)
 		return;
 
+	/* Configure P2SB VT-d originators (HPET and IOAPIC) */
+	pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, V_DEFAULT_HBDF);
+	pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, V_DEFAULT_IBDF);
+
 	if (igd_dev && igd_dev->enabled)
 		sa_set_mch_bar(&soc_gfxvt_mmio_descriptor, 1);