nb/intel/x4x: Switch to POSTCAR_STAGE
Change-Id: Ib7f0009bf024d1f09483e0cfc696d234ec78d267 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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@ -13,10 +13,7 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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ifneq ($(CONFIG_POSTCAR_STAGE),y)
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
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else
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cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
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postcar-y += ../car/p4-netburst/exit_car.S
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endif
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romstage-y += ../car/romstage.c
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@ -29,6 +29,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
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select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
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select CACHE_MRC_SETTINGS
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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config CBFS_SIZE
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hex
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@ -29,4 +29,6 @@ ramstage-y += ram_calc.c
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ramstage-y += gma.c
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ramstage-y += northbridge.c
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postcar-y += ram_calc.c
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endif
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@ -105,9 +105,10 @@ void *cbmem_top(void)
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#define ROMSTAGE_RAM_STACK_SIZE 0x5000
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/* setup_stack_and_mtrrs() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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void *setup_stack_and_mtrrs(void)
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/* platform_enter_postcar() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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@ -130,8 +131,7 @@ void *setup_stack_and_mtrrs(void)
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postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
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/* Save the number of MTRRs to setup. Return the stack location
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* pointing to the number of MTRRs.
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*/
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return postcar_commit_mtrrs(&pcf);
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run_postcar_phase(&pcf);
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/* We do not return here. */
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}
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