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nb/intel/x4x: Switch to POSTCAR_STAGE 

Change-Id: Ib7f0009bf024d1f09483e0cfc696d234ec78d267
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans 2018-06-03 10:49:11 +02:00
parent aa7cf5597b
commit 4ff675ebd0
4 changed files with 12 additions and 11 deletions
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5
src/cpu/intel/socket_LGA775/Makefile.inc
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@ -13,10 +13,7 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
else
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S postcar-y += ../car/p4-netburst/exit_car.S
endif
romstage-y += ../car/romstage.c romstage-y += ../car/romstage.c

2
src/northbridge/intel/x4x/Kconfig
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@ -29,6 +29,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select POSTCAR_STAGE
select POSTCAR_CONSOLE
config CBFS_SIZE config CBFS_SIZE
hex hex

2
src/northbridge/intel/x4x/Makefile.inc
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@ -29,4 +29,6 @@ ramstage-y += ram_calc.c
ramstage-y += gma.c ramstage-y += gma.c
ramstage-y += northbridge.c ramstage-y += northbridge.c
postcar-y += ram_calc.c
endif endif

14
src/northbridge/intel/x4x/ram_calc.c
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@ -105,9 +105,10 @@ void *cbmem_top(void)
#define ROMSTAGE_RAM_STACK_SIZE 0x5000 #define ROMSTAGE_RAM_STACK_SIZE 0x5000
/* setup_stack_and_mtrrs() determines the stack to use after /* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */ * cache-as-ram is torn down as well as the MTRR settings to use,
void *setup_stack_and_mtrrs(void) * and continues execution in postcar stage. */
void platform_enter_postcar(void)
{ {
struct postcar_frame pcf; struct postcar_frame pcf;
uintptr_t top_of_ram; uintptr_t top_of_ram;
@ -130,8 +131,7 @@ void *setup_stack_and_mtrrs(void)
postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
/* Save the number of MTRRs to setup. Return the stack location run_postcar_phase(&pcf);
* pointing to the number of MTRRs.
*/ /* We do not return here. */
return postcar_commit_mtrrs(&pcf);
} }