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soc/intel/baytrail: Improve CAR setup 

This patch does the following:
- improve the style by removing tabs in front of jmp addresses
- Make the code for zeroing variable MTRR more readable (copied from
  cpu/intel/car)
- Fetch PHYSMASK high from cpuid instead of Kconfig

Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Arthur Heymans 2018-11-29 13:57:14 +01:00 committed by Patrick Georgi
parent 90cca5422d
commit 4ff7921753
1 changed files with 50 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

73
src/soc/intel/baytrail/romstage/cache_as_ram.inc
View File

@ -32,7 +32,6 @@
#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) #define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE)
#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) #define CODE_CACHE_BASE (-CODE_CACHE_SIZE)
#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) #define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1))
#define CPU_PHYSMASK_HI ((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1)
#define NoEvictMod_MSR 0x2e0 #define NoEvictMod_MSR 0x2e0
#define BBL_CR_CTL3_MSR 0x11e #define BBL_CR_CTL3_MSR 0x11e
@ -68,27 +67,45 @@ wait_for_sipi:
rdmsr rdmsr
movzx %al, %ebx movzx %al, %ebx
/* First variable MTRR. */ /* First variable MTRR. */
movl $0x200, %ecx movl $MTRR_PHYS_BASE(0), %ecx
xorl %eax, %eax xorl %eax, %eax
xorl %edx, %edx xorl %edx, %edx
1: 1:
wrmsr wrmsr
inc %ecx inc %ecx
dec %ebx dec %ebx
jnz 1b jnz 1b
/* Zero out all fixed range and variable range MTRRs. */ /* Clear/disable fixed MTRRs */
movl $fixed_mtrr_table, %esi mov $fixed_mtrr_list_size, %ebx
movl $((fixed_mtrr_table_end - fixed_mtrr_table) >> 1), %edi xor %eax, %eax
xorl %eax, %eax xor %edx, %edx
xorl %edx, %edx
1: clear_fixed_mtrr:
movw (%esi), %bx add $-2, %ebx
movzx %bx, %ecx movzwl fixed_mtrr_list(%ebx), %ecx
wrmsr wrmsr
add $2, %esi jnz clear_fixed_mtrr
dec %edi
jnz 1b /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */
movl $0x80000008, %eax
cpuid
movb %al, %cl
sub $32, %cl
movl $1, %edx
shl %cl, %edx
subl $1, %edx
/* Preload high word of address mask (in %edx) for Variable
* MTRRs 0 and 1.
*/
addrsize_set_high:
xorl %eax, %eax
movl $MTRR_PHYS_MASK(0), %ecx
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
wrmsr
post_code(0x23) post_code(0x23)
/* Set Cache-as-RAM base address. */ /* Set Cache-as-RAM base address. */
@ -100,8 +117,8 @@ wait_for_sipi:
post_code(0x24) post_code(0x24)
/* Set Cache-as-RAM mask. */ /* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr wrmsr
post_code(0x25) post_code(0x25)
@ -111,9 +128,9 @@ wait_for_sipi:
xorl %edx, %edx xorl %edx, %edx
wrmsr wrmsr
movl $(MTRR_PHYS_MASK(1)), %ecx movl $MTRR_PHYS_MASK(1), %ecx
movl $(CODE_CACHE_MASK | MTRR_PHYS_MASK_VALID), %eax rdmsr
movl $CPU_PHYSMASK_HI, %edx movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr wrmsr
/* Enable MTRR. */ /* Enable MTRR. */
@ -272,10 +289,16 @@ __main:
hlt hlt
jmp .Lhlt jmp .Lhlt
/* Fixed MTRRs */ fixed_mtrr_list:
fixed_mtrr_table: .word MTRR_FIX_64K_00000
.word 0x250, 0x258, 0x259 .word MTRR_FIX_16K_80000
.word 0x268, 0x269, 0x26A .word MTRR_FIX_16K_A0000
.word 0x26B, 0x26C, 0x26D .word MTRR_FIX_4K_C0000
.word 0x26E, 0x26F .word MTRR_FIX_4K_C8000
fixed_mtrr_table_end: .word MTRR_FIX_4K_D0000
.word MTRR_FIX_4K_D8000
.word MTRR_FIX_4K_E0000
.word MTRR_FIX_4K_E8000
.word MTRR_FIX_4K_F0000
.word MTRR_FIX_4K_F8000
fixed_mtrr_list_size = . - fixed_mtrr_list