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Reduce duplicate definition in CAR code. 

Macros for the register addresses for the MTRR MSRs are already defined
in include/cpu/x86/car.h. This patch uses those macros instead of
creating a second instance of that same data.

I also added a few macros to the amd mtrr.h to make the MSR naming more
consistent.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Warren Turkal 2010-10-12 06:13:40 +00:00
parent 9c814d2e9e
commit 4ffde94c4e
4 changed files with 111 additions and 43 deletions
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55
src/cpu/amd/car/cache_as_ram.inc
View File

@ -155,7 +155,7 @@ enable_fixed_mtrr_dram_modify:
/* Clear all MTRRs. */ /* Clear all MTRRs. */
xorl %edx, %edx xorl %edx, %edx
movl $fixed_mtrr_msr, %esi movl $all_mtrr_msrs, %esi
clear_fixed_var_mtrr: clear_fixed_var_mtrr:
lodsl (%esi), %eax lodsl (%esi), %eax
@ -396,23 +396,48 @@ CAR_FAM10_ap_out:
post_code(0xaf) /* Should never see this POST code. */ post_code(0xaf) /* Should never see this POST code. */
fixed_mtrr_msr: all_mtrr_msrs:
.long 0x250, 0x258, 0x259 /* fixed MTRR MSRs */
.long 0x268, 0x269, 0x26A .long MTRRfix64K_00000_MSR
.long 0x26B, 0x26C, 0x26D .long MTRRfix16K_80000_MSR
.long 0x26E, 0x26F .long MTRRfix16K_A0000_MSR
.long MTRRfix4K_C0000_MSR
.long MTRRfix4K_C8000_MSR
.long MTRRfix4K_D0000_MSR
.long MTRRfix4K_D8000_MSR
.long MTRRfix4K_E0000_MSR
.long MTRRfix4K_E8000_MSR
.long MTRRfix4K_F0000_MSR
.long MTRRfix4K_F8000_MSR
var_mtrr_msr: /* var MTRR MSRs */
.long 0x200, 0x201, 0x202, 0x203 .long MTRRphysBase_MSR(0)
.long 0x204, 0x205, 0x206, 0x207 .long MTRRphysMask_MSR(0)
.long 0x208, 0x209, 0x20A, 0x20B .long MTRRphysBase_MSR(1)
.long 0x20C, 0x20D, 0x20E, 0x20F .long MTRRphysMask_MSR(1)
.long MTRRphysBase_MSR(2)
.long MTRRphysMask_MSR(2)
.long MTRRphysBase_MSR(3)
.long MTRRphysMask_MSR(3)
.long MTRRphysBase_MSR(4)
.long MTRRphysMask_MSR(4)
.long MTRRphysBase_MSR(5)
.long MTRRphysMask_MSR(5)
.long MTRRphysBase_MSR(6)
.long MTRRphysMask_MSR(6)
.long MTRRphysBase_MSR(7)
.long MTRRphysMask_MSR(7)
var_iorr_msr: /* Variable IORR MTRR MSRs */
.long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 .long IORRBase_MSR(0)
.long IORRMask_MSR(0)
.long IORRBase_MSR(1)
.long IORRMask_MSR(1)
/* Top of memory MTRR MSRs */
.long TOP_MEM_MSR
.long TOP_MEM2_MSR
mem_top:
.long 0xC001001A, 0xC001001D
.long 0x000 /* NULL, end of table */ .long 0x000 /* NULL, end of table */
cache_as_ram_setup_out: cache_as_ram_setup_out:

43
src/cpu/intel/car/cache_as_ram.inc
View File

@ -115,7 +115,7 @@ NotHtProcessor:
/* Clear all MTRRs. */ /* Clear all MTRRs. */
xorl %edx, %edx xorl %edx, %edx
movl $fixed_mtrr_msr, %esi movl $all_mtrr_msrs, %esi
clear_fixed_var_mtrr: clear_fixed_var_mtrr:
lodsl (%esi), %eax lodsl (%esi), %eax
@ -128,17 +128,38 @@ clear_fixed_var_mtrr:
jmp clear_fixed_var_mtrr jmp clear_fixed_var_mtrr
fixed_mtrr_msr: all_mtrr_msrs:
.long 0x250, 0x258, 0x259 /* fixed MTRR MSRs */
.long 0x268, 0x269, 0x26A .long MTRRfix64K_00000_MSR
.long 0x26B, 0x26C, 0x26D .long MTRRfix16K_80000_MSR
.long 0x26E, 0x26F .long MTRRfix16K_A0000_MSR
.long MTRRfix4K_C0000_MSR
.long MTRRfix4K_C8000_MSR
.long MTRRfix4K_D0000_MSR
.long MTRRfix4K_D8000_MSR
.long MTRRfix4K_E0000_MSR
.long MTRRfix4K_E8000_MSR
.long MTRRfix4K_F0000_MSR
.long MTRRfix4K_F8000_MSR
/* var MTRR MSRs */
.long MTRRphysBase_MSR(0)
.long MTRRphysMask_MSR(0)
.long MTRRphysBase_MSR(1)
.long MTRRphysMask_MSR(1)
.long MTRRphysBase_MSR(2)
.long MTRRphysMask_MSR(2)
.long MTRRphysBase_MSR(3)
.long MTRRphysMask_MSR(3)
.long MTRRphysBase_MSR(4)
.long MTRRphysMask_MSR(4)
.long MTRRphysBase_MSR(5)
.long MTRRphysMask_MSR(5)
.long MTRRphysBase_MSR(6)
.long MTRRphysMask_MSR(6)
.long MTRRphysBase_MSR(7)
.long MTRRphysMask_MSR(7)
var_mtrr_msr:
.long 0x200, 0x201, 0x202, 0x203
.long 0x204, 0x205, 0x206, 0x207
.long 0x208, 0x209, 0x20A, 0x20B
.long 0x20C, 0x20D, 0x20E, 0x20F
.long 0x000 /* NULL, end of table */ .long 0x000 /* NULL, end of table */
clear_fixed_var_mtrr_out: clear_fixed_var_mtrr_out:

43
src/cpu/via/car/cache_as_ram.inc
View File

@ -47,7 +47,7 @@ CacheAsRam:
/* Clear all MTRRs. */ /* Clear all MTRRs. */
xorl %edx, %edx xorl %edx, %edx
movl $fixed_mtrr_msr, %esi movl $all_mtrr_msrs, %esi
clear_fixed_var_mtrr: clear_fixed_var_mtrr:
lodsl (%esi), %eax lodsl (%esi), %eax
@ -60,17 +60,38 @@ clear_fixed_var_mtrr:
jmp clear_fixed_var_mtrr jmp clear_fixed_var_mtrr
fixed_mtrr_msr: all_mtrr_msrs:
.long 0x250, 0x258, 0x259 /* fixed MTRR MSRs */
.long 0x268, 0x269, 0x26A .long MTRRfix64K_00000_MSR
.long 0x26B, 0x26C, 0x26D .long MTRRfix16K_80000_MSR
.long 0x26E, 0x26F .long MTRRfix16K_A0000_MSR
.long MTRRfix4K_C0000_MSR
.long MTRRfix4K_C8000_MSR
.long MTRRfix4K_D0000_MSR
.long MTRRfix4K_D8000_MSR
.long MTRRfix4K_E0000_MSR
.long MTRRfix4K_E8000_MSR
.long MTRRfix4K_F0000_MSR
.long MTRRfix4K_F8000_MSR
/* var MTRR MSRs */
.long MTRRphysBase_MSR(0)
.long MTRRphysMask_MSR(0)
.long MTRRphysBase_MSR(1)
.long MTRRphysMask_MSR(1)
.long MTRRphysBase_MSR(2)
.long MTRRphysMask_MSR(2)
.long MTRRphysBase_MSR(3)
.long MTRRphysMask_MSR(3)
.long MTRRphysBase_MSR(4)
.long MTRRphysMask_MSR(4)
.long MTRRphysBase_MSR(5)
.long MTRRphysMask_MSR(5)
.long MTRRphysBase_MSR(6)
.long MTRRphysMask_MSR(6)
.long MTRRphysBase_MSR(7)
.long MTRRphysMask_MSR(7)
var_mtrr_msr:
.long 0x200, 0x201, 0x202, 0x203
.long 0x204, 0x205, 0x206, 0x207
.long 0x208, 0x209, 0x20A, 0x20B
.long 0x20C, 0x20D, 0x20E, 0x20F
.long 0x000 /* NULL, end of table */ .long 0x000 /* NULL, end of table */
clear_fixed_var_mtrr_out: clear_fixed_var_mtrr_out:

13
src/include/cpu/amd/mtrr.h
View File

@ -21,12 +21,13 @@
#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5)) #define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0)) #define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
#define IORR0_BASE 0xC0010016 #define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
#define IORR0_MASK 0xC0010017 #define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
#define IORR1_BASE 0xC0010018
#define IORR1_MASK 0xC0010019 #define TOP_MEM_MSR 0xC001001A
#define TOP_MEM 0xC001001A #define TOP_MEM2_MSR 0xC001001D
#define TOP_MEM2 0xC001001D #define TOP_MEM TOP_MEM_MSR
#define TOP_MEM2 TOP_MEM2_MSR
#define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)