indent
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
97c4947ec9
commit
500497fc34
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@ -40,19 +40,21 @@ static void soft_reset(void)
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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}
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static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
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(0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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else {
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
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(0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
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} else {
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/* Ensure the CPU has controll of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
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(1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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}
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@ -61,7 +63,8 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
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if (is_cpu_pre_c0()) {
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udelay(800);
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
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(1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
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udelay(90);
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}
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}
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@ -71,7 +74,8 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
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*
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*/
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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static unsigned int generate_row(uint8_t node, uint8_t row,
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uint8_t maxnodes)
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{
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/* Routing Table Node i
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*
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@ -95,25 +99,25 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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* [3] Route to Link 2
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*/
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uint32_t ret=0x00010101; /* default row entry */
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uint32_t ret = 0x00010101; /* default row entry */
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static const unsigned int rows_2p[2][2] = {
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{ 0x00030101, 0x00010202 },
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{ 0x00010202, 0x00030101 }
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{0x00030101, 0x00010202},
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{0x00010202, 0x00030101}
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};
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static const unsigned int rows_4p[4][4] = {
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{ 0x00070101, 0x00010202, 0x00030404, 0x00010204 },
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{ 0x00010202, 0x000b0101, 0x00010208, 0x00030808 },
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{ 0x00030808, 0x00010208, 0x000b0101, 0x00010202 },
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{ 0x00010204, 0x00030404, 0x00010202, 0x00070101 }
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{0x00070101, 0x00010202, 0x00030404, 0x00010204},
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{0x00010202, 0x000b0101, 0x00010208, 0x00030808},
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{0x00030808, 0x00010208, 0x000b0101, 0x00010202},
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{0x00010204, 0x00030404, 0x00010202, 0x00070101}
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};
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if (!(node>=maxnodes || row>=maxnodes)) {
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if (maxnodes==2)
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ret=rows_2p[node][row];
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if (maxnodes==4)
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ret=rows_4p[node][row];
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if (!(node >= maxnodes || row >= maxnodes)) {
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if (maxnodes == 2)
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ret = rows_2p[node][row];
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if (maxnodes == 4)
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ret = rows_4p[node][row];
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}
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return ret;
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@ -124,9 +128,9 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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#define SMBUS_HUB 0x18
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unsigned device=(ctrl->channel0[0])>>8;
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smbus_write_byte(SMBUS_HUB , 0x01, device);
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smbus_write_byte(SMBUS_HUB , 0x03, 0);
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unsigned device = (ctrl->channel0[0]) >> 8;
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smbus_write_byte(SMBUS_HUB, 0x01, device);
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smbus_write_byte(SMBUS_HUB, 0x03, 0);
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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@ -143,7 +147,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "sdram/generic_sdram.c"
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#include "resourcemap.c" /* quartet does not want the default */
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#include "resourcemap.c" /* quartet does not want the default */
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#define RC0 ((1<<1)<<8)
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#define RC1 ((1<<2)<<8)
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@ -159,57 +163,57 @@ static void main(void)
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{
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static const struct mem_controller cpu[] = {
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
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.channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
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},
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = {RC0 | DIMM0, RC0 | DIMM2, 0, 0},
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.channel1 = {RC0 | DIMM1, RC0 | DIMM3, 0, 0},
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},
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{
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.node_id = 1,
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = { RC1|DIMM0, RC1|DIMM2, 0, 0 },
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.channel1 = { RC1|DIMM1, RC1|DIMM3, 0, 0 },
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},
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.node_id = 1,
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = {RC1 | DIMM0, RC1 | DIMM2, 0, 0},
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.channel1 = {RC1 | DIMM1, RC1 | DIMM3, 0, 0},
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},
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{
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.node_id = 2,
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.f0 = PCI_DEV(0, 0x1a, 0),
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.f1 = PCI_DEV(0, 0x1a, 1),
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.f2 = PCI_DEV(0, 0x1a, 2),
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.f3 = PCI_DEV(0, 0x1a, 3),
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.channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
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.channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
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},
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.node_id = 2,
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.f0 = PCI_DEV(0, 0x1a, 0),
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.f1 = PCI_DEV(0, 0x1a, 1),
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.f2 = PCI_DEV(0, 0x1a, 2),
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.f3 = PCI_DEV(0, 0x1a, 3),
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.channel0 = {RC2 | DIMM0, RC2 | DIMM2, 0, 0},
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.channel1 = {RC2 | DIMM1, RC2 | DIMM3, 0, 0},
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},
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{
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.node_id = 3,
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.f0 = PCI_DEV(0, 0x1b, 0),
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.f1 = PCI_DEV(0, 0x1b, 1),
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.f2 = PCI_DEV(0, 0x1b, 2),
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.f3 = PCI_DEV(0, 0x1b, 3),
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.channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
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.channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
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}
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.node_id = 3,
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.f0 = PCI_DEV(0, 0x1b, 0),
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.f1 = PCI_DEV(0, 0x1b, 1),
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.f2 = PCI_DEV(0, 0x1b, 2),
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.f3 = PCI_DEV(0, 0x1b, 3),
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.channel0 = {RC3 | DIMM0, RC3 | DIMM2, 0, 0},
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.channel1 = {RC3 | DIMM1, RC3 | DIMM3, 0, 0},
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}
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};
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int needs_reset;
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enable_lapic();
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init_timer();
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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}
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distinguish_cpu_resets();
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if (!boot_cpu()) {
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stop_this_cpu();
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}
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pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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@ -228,7 +232,7 @@ static void main(void)
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dump_spd_registers(&cpu[0]);
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#endif
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
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#if 0
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dump_pci_devices();
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@ -23,25 +23,25 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
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static int spd_read_byte(unsigned device, unsigned address)
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{
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static const unsigned char infinion_512mb_pc2700[0x80] = {
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0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00,
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0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00,
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0x04, 0x60, 0x70, 0x02, 0x82, 0x04, 0x04, 0x01,
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0x0e, 0x04, 0x0c, 0x01, 0x02, 0x26, 0xc0, 0x75,
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0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x80,
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0x75, 0x75, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
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0x75, 0x75, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47,
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0xc1, 0x49, 0x4e, 0x46, 0x49, 0x4e, 0x45, 0x4f,
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0x53, 0x37, 0x32, 0x44, 0x36, 0x34, 0x33, 0x30,
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0x30, 0x47, 0x42, 0x52, 0x36, 0x42, 0x20, 0x20,
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0xc1, 0x49, 0x4e, 0x46, 0x49, 0x4e, 0x45, 0x4f,
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0x53, 0x37, 0x32, 0x44, 0x36, 0x34, 0x33, 0x30,
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0x30, 0x47, 0x42, 0x52, 0x36, 0x42, 0x20, 0x20,
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0x20, 0x20, 0x20, 0x02, 0x0a, 0x03, 0x21, 0x0d,
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0x3d, 0x89, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x3d, 0x89, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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};
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if ( address >= 0x80 )
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if (address >= 0x80)
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return -1;
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/* This code is AMD quartet specific.
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@ -54,10 +54,9 @@ static int spd_read_byte(unsigned device, unsigned address)
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*/
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device &= 0xff;
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if (device==DIMM0 || device==DIMM1) {
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if (device == DIMM0 || device == DIMM1) {
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return infinion_512mb_pc2700[address];
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}
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return -1;
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}
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