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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2004-04-28 08:08:06 +00:00
parent 97c4947ec9
commit 500497fc34
2 changed files with 77 additions and 74 deletions
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66
src/mainboard/amd/quartet/auto.c
View File

@ -46,13 +46,15 @@ static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
else {
outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@ -61,7 +63,8 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
@ -71,7 +74,8 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
*
*/
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
static unsigned int generate_row(uint8_t node, uint8_t row,
uint8_t maxnodes)
{
/* Routing Table Node i
*
@ -95,25 +99,25 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
* [3] Route to Link 2
*/
uint32_t ret=0x00010101; /* default row entry */
uint32_t ret = 0x00010101; /* default row entry */
static const unsigned int rows_2p[2][2] = {
{ 0x00030101, 0x00010202 },
{ 0x00010202, 0x00030101 }
{0x00030101, 0x00010202},
{0x00010202, 0x00030101}
};
static const unsigned int rows_4p[4][4] = {
{ 0x00070101, 0x00010202, 0x00030404, 0x00010204 },
{ 0x00010202, 0x000b0101, 0x00010208, 0x00030808 },
{ 0x00030808, 0x00010208, 0x000b0101, 0x00010202 },
{ 0x00010204, 0x00030404, 0x00010202, 0x00070101 }
{0x00070101, 0x00010202, 0x00030404, 0x00010204},
{0x00010202, 0x000b0101, 0x00010208, 0x00030808},
{0x00030808, 0x00010208, 0x000b0101, 0x00010202},
{0x00010204, 0x00030404, 0x00010202, 0x00070101}
};
if (!(node>=maxnodes || row>=maxnodes)) {
if (maxnodes==2)
ret=rows_2p[node][row];
if (maxnodes==4)
ret=rows_4p[node][row];
if (!(node >= maxnodes || row >= maxnodes)) {
if (maxnodes == 2)
ret = rows_2p[node][row];
if (maxnodes == 4)
ret = rows_4p[node][row];
}
return ret;
@ -124,9 +128,9 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
unsigned device=(ctrl->channel0[0])>>8;
smbus_write_byte(SMBUS_HUB , 0x01, device);
smbus_write_byte(SMBUS_HUB , 0x03, 0);
unsigned device = (ctrl->channel0[0]) >> 8;
smbus_write_byte(SMBUS_HUB, 0x01, device);
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
static inline int spd_read_byte(unsigned device, unsigned address)
@ -164,8 +168,8 @@ static void main(void)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
.channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
.channel0 = {RC0 | DIMM0, RC0 | DIMM2, 0, 0},
.channel1 = {RC0 | DIMM1, RC0 | DIMM3, 0, 0},
},
{
.node_id = 1,
@ -173,8 +177,8 @@ static void main(void)
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { RC1|DIMM0, RC1|DIMM2, 0, 0 },
.channel1 = { RC1|DIMM1, RC1|DIMM3, 0, 0 },
.channel0 = {RC1 | DIMM0, RC1 | DIMM2, 0, 0},
.channel1 = {RC1 | DIMM1, RC1 | DIMM3, 0, 0},
},
{
.node_id = 2,
@ -182,8 +186,8 @@ static void main(void)
.f1 = PCI_DEV(0, 0x1a, 1),
.f2 = PCI_DEV(0, 0x1a, 2),
.f3 = PCI_DEV(0, 0x1a, 3),
.channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
.channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
.channel0 = {RC2 | DIMM0, RC2 | DIMM2, 0, 0},
.channel1 = {RC2 | DIMM1, RC2 | DIMM3, 0, 0},
},
{
.node_id = 3,
@ -191,8 +195,8 @@ static void main(void)
.f1 = PCI_DEV(0, 0x1b, 1),
.f2 = PCI_DEV(0, 0x1b, 2),
.f3 = PCI_DEV(0, 0x1b, 3),
.channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
.channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
.channel0 = {RC3 | DIMM0, RC3 | DIMM2, 0, 0},
.channel1 = {RC3 | DIMM1, RC3 | DIMM3, 0, 0},
}
};
int needs_reset;
@ -228,7 +232,7 @@ static void main(void)
dump_spd_registers(&cpu[0]);
#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();

5
src/mainboard/amd/quartet/fakespd.c
View File

@ -41,7 +41,7 @@ static int spd_read_byte(unsigned device, unsigned address)
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
if ( address >= 0x80 )
if (address >= 0x80)
return -1;
/* This code is AMD quartet specific.
@ -54,10 +54,9 @@ static int spd_read_byte(unsigned device, unsigned address)
*/
device &= 0xff;
if (device==DIMM0 || device==DIMM1) {
if (device == DIMM0 || device == DIMM1) {
return infinion_512mb_pc2700[address];
}
return -1;
}