From 50134eccbdf4878f03e64b8085832a86c5b928f0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 9 Jun 2021 04:14:50 +0530 Subject: [PATCH] soc/intel/alderlake: Make use of is_devfn_enabled() function 1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on ADL. Change-Id: I92671992ec14fd2adca1635b0791ac8b456332e9 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/55292 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/acpi.c | 11 ++--- src/soc/intel/alderlake/fsp_params.c | 25 ++++------ src/soc/intel/alderlake/romstage/fsp_params.c | 48 +++++-------------- 3 files changed, 25 insertions(+), 59 deletions(-) diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 04d2a296fe..23d2a262e6 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -172,11 +172,10 @@ uint32_t soc_read_sci_irq_select(void) static unsigned long soc_fill_dmar(unsigned long current) { - const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; const bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; - if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) { + if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); @@ -185,11 +184,10 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } - const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); const uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; const bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; - if (is_dev_enabled(ipu_dev) && ipuvtbar && ipuvten) { + if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); @@ -200,8 +198,7 @@ static unsigned long soc_fill_dmar(unsigned long current) /* TCSS Thunderbolt root ports */ for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { - const struct device *const tbt_dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); - if (is_dev_enabled(tbt_dev)) { + if (is_devfn_enabled(SA_DEVFN_TBT(i))) { const uint64_t tbtbar = MCHBAR64(TBTxBAR(i)) & VTBAR_MASK; const bool tbten = MCHBAR32(TBTxBAR(i)) & VTBAR_ENABLED; if (tbtbar && tbten) { @@ -235,7 +232,7 @@ static unsigned long soc_fill_dmar(unsigned long current) } /* Add RMRR entry */ - if (is_dev_enabled(igfx_dev)) { + if (is_devfn_enabled(SA_DEVFN_IGD)) { const unsigned long tmp = current; current += acpi_create_dmar_rmrr(current, 0, sa_get_gsm_base(), sa_get_tolud_base() - 1); diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 22329f2397..78162311d5 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -102,8 +102,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->GraphicsConfigPtr = (uintptr_t)vbt_get(); /* Check if IGD is present and fill Graphics init param accordingly */ - dev = pcidev_path_on_root(SA_DEVFN_IGD); - params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); + params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); params->LidStatus = CONFIG(RUN_FSP_GOP); /* Use coreboot MP PPI services if Kconfig is enabled */ @@ -195,8 +194,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; /* SATA */ - dev = pcidev_path_on_root(PCH_DEVFN_SATA); - params->SataEnable = is_dev_enabled(dev); + params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); if (params->SataEnable) { params->SataMode = config->SataMode; params->SataSalpSupport = config->SataSalpSupport; @@ -229,19 +227,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* Enable TCPU for processor thermal control */ - dev = pcidev_path_on_root(SA_DEVFN_DPTF); - params->Device4Enable = is_dev_enabled(dev); + params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); /* Set TccActivationOffset */ params->TccActivationOffset = config->tcc_offset; /* LAN */ - dev = pcidev_path_on_root(PCH_DEVFN_GBE); - params->PchLanEnable = is_dev_enabled(dev); + params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); /* CNVi */ - dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); - params->CnviMode = is_dev_enabled(dev); + params->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); params->CnviBtCore = config->CnviBtCore; params->CnviBtAudioOffload = config->CnviBtAudioOffload; /* Assert if CNVi BT is enabled without CNVi being enabled. */ @@ -250,15 +245,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) assert(params->CnviBtCore || !params->CnviBtAudioOffload); /* VMD */ - dev = pcidev_path_on_root(SA_DEVFN_VMD); - params->VmdEnable = is_dev_enabled(dev); + params->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD); /* THC */ - dev = pcidev_path_on_root(PCH_DEVFN_THC0); - params->ThcPort0Assignment = is_dev_enabled(dev) ? THC_0 : THC_NONE; - - dev = pcidev_path_on_root(PCH_DEVFN_THC1); - params->ThcPort1Assignment = is_dev_enabled(dev) ? THC_1 : THC_NONE; + params->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; + params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 3892f25477..a2b576372c 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -67,14 +67,9 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { - const struct device *dev; unsigned int i; - dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev)) - m_cfg->InternalGfx = 1; - else - m_cfg->InternalGfx = 0; + m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD); /* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */ m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? IGD_SM_60MB : 0; @@ -129,14 +124,12 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Disable Lock PCU Thermal Management registers */ m_cfg->LockPTMregs = 0; /* Enable SMBus controller */ - dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); - m_cfg->SmbusEnable = is_dev_enabled(dev); + m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS); /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); - m_cfg->PchHdaEnable = is_dev_enabled(dev); + m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA); m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; /* @@ -175,39 +168,24 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, CONFIG_MAX_CPU_ROOT_PORTS); /* ISH */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); - m_cfg->PchIshEnable = is_dev_enabled(dev); + m_cfg->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH); /* Tcss USB */ - dev = pcidev_path_on_root(SA_DEVFN_TCSS_XHCI); - m_cfg->TcssXhciEn = is_dev_enabled(dev); - - dev = pcidev_path_on_root(SA_DEVFN_TCSS_XDCI); - m_cfg->TcssXdciEn = is_dev_enabled(dev); + m_cfg->TcssXhciEn = is_devfn_enabled(SA_DEVFN_TCSS_XHCI); + m_cfg->TcssXdciEn = is_devfn_enabled(SA_DEVFN_TCSS_XDCI); /* TCSS DMA */ - dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); - m_cfg->TcssDma0En = is_dev_enabled(dev); - - dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); - m_cfg->TcssDma1En = is_dev_enabled(dev); + m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0); + m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1); /* USB4/TBT */ - dev = pcidev_path_on_root(SA_DEVFN_TBT0); - m_cfg->TcssItbtPcie0En = is_dev_enabled(dev); - - dev = pcidev_path_on_root(SA_DEVFN_TBT1); - m_cfg->TcssItbtPcie1En = is_dev_enabled(dev); - - dev = pcidev_path_on_root(SA_DEVFN_TBT2); - m_cfg->TcssItbtPcie2En = is_dev_enabled(dev); - - dev = pcidev_path_on_root(SA_DEVFN_TBT3); - m_cfg->TcssItbtPcie3En = is_dev_enabled(dev); + m_cfg->TcssItbtPcie0En = is_devfn_enabled(SA_DEVFN_TBT0); + m_cfg->TcssItbtPcie1En = is_devfn_enabled(SA_DEVFN_TBT1); + m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2); + m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3); /* IPU */ - dev = pcidev_path_on_root(SA_DEVFN_IPU); - m_cfg->SaIpuEnable = is_dev_enabled(dev); + m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU); /* VT-d config */ m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS;