mb/google/nissa: Remove SI_ME subregions

The SI_ME subregions were added to support using the CSE stitching tools
(cse_serger). Use of the stitching tools has been reverted and probably
won't be re-enabled soon, so the subregions are not currently used by
anything. They also don't match the actual region sizes chosen by the
FIT tool, so remove them to avoid confusion. The other option would be
to manually keep them in sync with the sizes chosen by the FIT tool, but
this would be extra manual effort without much benefit.

BUG=None
TEST=Build and boot on nivviks

Change-Id: I993e07a060445ab8de1b0e40a023e8248867c53c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69540
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>

src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd

@@ -1,13 +1,7 @@
 FLASH 16M {
 	SI_ALL 3776K {
 		SI_DESC 4K
-		SI_ME {
-			CSE_LAYOUT 8K
-			CSE_RO 1360K
-			CSE_DATA 420K
-			# 64-KiB aligned to optimize RW erases during CSE update.
-			CSE_RW 1984K
-		}
+		SI_ME
 	}
 	SI_BIOS 12608K {
 		RW_SECTION_A 4180K {

src/mainboard/google/brya/chromeos-nissa-16MiB.fmd

@@ -1,13 +1,7 @@
 FLASH 16M {
 	SI_ALL 3776K {
 		SI_DESC 4K
-		SI_ME {
-			CSE_LAYOUT 8K
-			CSE_RO 1360K
-			CSE_DATA 420K
-			# 64-KiB aligned to optimize RW erases during CSE update.
-			CSE_RW 1984K
-		}
+		SI_ME
 	}
 	SI_BIOS 12608K {
 		RW_SECTION_A 3668K {

src/mainboard/google/brya/chromeos-nissa-32MiB.fmd

@@ -1,13 +1,7 @@
 FLASH 32M {
 	SI_ALL 3776K {
 		SI_DESC 4K
-		SI_ME {
-			CSE_LAYOUT 8K
-			CSE_RO 1360K
-			CSE_DATA 420K
-			# 64-KiB aligned to optimize RW erases during CSE update.
-			CSE_RW 1984K
-		}
+		SI_ME
 	}
 	SI_BIOS 28992K {
 		RW_SECTION_A 4344K {