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mb/google/sarien: Set touchpad/screen IRQs to LEVEL vs EDGE 

Ensure the GPIOs themselves are configured as level triggered, as well
as the devicetree entiures. I2C-HID spec requires LEVEL trigger, and the
drivers (both Linux and Windows) work better with LEVEL vs EDGE trigger.

TEST=tested with rest of patch train

Change-Id: I4fba55c938f401876798c2b32c5922523f32180f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Matt DeVillier 2023-02-24 10:28:58 -06:00
parent b4bf865359
commit 50143cfb22
4 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -324,7 +324,7 @@ chip soc/intel/cannonlake
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""ELAN0000"" register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad"" register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
register "detect" = "1" register "detect" = "1"
device i2c 2c on end device i2c 2c on end
end end

2
src/mainboard/google/sarien/variants/arcada/gpio.c
View File

@ -39,7 +39,7 @@ static const struct pad_config gpio_table[] = {
/* CORE_VID1 */ /* CORE_VID1 */
/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* VRALERT# */ PAD_NC(GPP_B2, NONE),
/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ LEVEL, INVERT), /* TOUCHPAD_INTR# */
/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
/* LAN_CLKREQ_CPU_N */ /* LAN_CLKREQ_CPU_N */
/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),

4
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -338,7 +338,7 @@ chip soc/intel/cannonlake
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""MLFS0000"" register "hid" = ""MLFS0000""
register "desc" = ""Melfas Touchscreen"" register "desc" = ""Melfas Touchscreen""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
register "probed" = "1" register "probed" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
register "reset_delay_ms" = "10" register "reset_delay_ms" = "10"
@ -354,7 +354,7 @@ chip soc/intel/cannonlake
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""ELAN0000"" register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad"" register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
register "detect" = "1" register "detect" = "1"
device i2c 2c on end device i2c 2c on end
end end

4
src/mainboard/google/sarien/variants/sarien/gpio.c
View File

@ -34,7 +34,7 @@ static const struct pad_config gpio_table[] = {
/* CORE_VID1 */ /* CORE_VID1 */
/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* VRALERT# */ PAD_NC(GPP_B2, NONE),
/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ LEVEL, INVERT), /* TOUCHPAD_INTR# */
/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */
@ -81,7 +81,7 @@ static const struct pad_config gpio_table[] = {
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* UART2_RTS# */ PAD_NC(GPP_C22, NONE),
/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, /* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* TS_INT# */ LEVEL, INVERT), /* TS_INT# */
/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, /* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */