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Remove google/urara mainboard 

This board never really existed and nobody has any hardware left over
for it.

Change-Id: Icdba4f5209725995e4a55dcdbc299a9e91a5869a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Julius Werner 2019-10-30 16:08:40 -07:00 committed by Patrick Georgi
parent 29c8fa4769
commit 5027ecfb19
12 changed files with 0 additions and 632 deletions
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55
src/mainboard/google/urara/Kconfig
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@ -1,55 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2014 Imagination Technologies
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
if BOARD_GOOGLE_URARA
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_512
select SPI_FLASH_WINBOND
select CPU_IMGTEC_PISTACHIO
select COMMON_CBFS_SPI_WRAPPER
select SPI_FLASH
config MAINBOARD_DIR
string
default "google/urara"
config MAINBOARD_PART_NUMBER
string
default "ImgTec Pistachio Virtual Platform"
config BOOTBLOCK_MAINBOARD_INIT
string
default "mainboard/google/urara/bootblock.c"
config DRAM_SIZE_MB
int
default 256
config TTYS0_LCS
int
default 3
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0xB8101500
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 1
endif

2
src/mainboard/google/urara/Kconfig.name
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config BOARD_GOOGLE_URARA
bool "Urara"

25
src/mainboard/google/urara/Makefile.inc
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#
# This file is part of the coreboot project.
#
# Copyright 2014 Imagination Technologies Ltd.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
bootblock-y += boardid.c
ramstage-y += boardid.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

5
src/mainboard/google/urara/board_info.txt
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@ -1,5 +0,0 @@
Vendor name: Google
Board name: Urara Imgtec Pistachio reference board
Category: eval
ROM protocol: SPI
ROM socketed: n

98
src/mainboard/google/urara/boardid.c
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@ -1,98 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdlib.h>
#include <string.h>
#include <boardid.h>
#include <cbfs.h>
#include <console/console.h>
#include "mainboard/google/urara/urara_boardid.h"
/* Name of the CBFS file were the board ID string is read from. */
#define CBFS_BOARD_ID_FILE_NAME "board_id"
const struct bid_map {
const char *board_name;
uint8_t board_id;
struct board_hw hardware;
} board_id_map[] = {
{"urara", URARA_BOARD_ID_BUB, {0} },
{"buranku", URARA_BOARD_ID_BURANKU, {3} },
{"derwent", URARA_BOARD_ID_DERWENT, {3} },
{"jaguar", URARA_BOARD_ID_JAGUAR, {3} },
{"kennet", URARA_BOARD_ID_KENNET, {3} },
{"space", URARA_BOARD_ID_SPACE, {3} },
};
static int cached_board_id = -1;
static uint8_t retrieve_board_id(void)
{
const char *board_id_file_name = CBFS_BOARD_ID_FILE_NAME;
char *file_contents;
int i;
size_t length;
file_contents = cbfs_boot_map_with_leak(board_id_file_name,
CBFS_TYPE_RAW, &length);
if (!file_contents) {
printk(BIOS_WARNING,
"board_id: failed to locate file '%s'\n",
board_id_file_name);
return 0;
}
for (i = 0; i < ARRAY_SIZE(board_id_map); i++) {
const struct bid_map *entry = board_id_map + i;
if ((strlen(entry->board_name) == length) &&
!strncmp(entry->board_name, file_contents, length)) {
printk(BIOS_INFO, "board_id: name '%s', ID %d\n",
entry->board_name, entry->board_id);
return entry->board_id;
}
}
printk(BIOS_WARNING, "board_id: no match for board name '%.*s'\n",
length, file_contents);
printk(BIOS_WARNING, "board_id: will use default board ID 0\n");
return 0;
}
const struct board_hw *board_get_hw(void)
{
int i;
uint8_t bid = board_id();
for (i = 0; i < ARRAY_SIZE(board_id_map); i++) {
if (bid == board_id_map[i].board_id)
return &(board_id_map[i].hardware);
}
return 0;
}
uint32_t board_id(void)
{
if (cached_board_id == -1)
cached_board_id = retrieve_board_id();
return cached_board_id;
}

248
src/mainboard/google/urara/bootblock.c
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@ -1,248 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/mmio.h>
#include <stdint.h>
#include <soc/clocks.h>
#include <assert.h>
#include <boardid.h>
#include "urara_boardid.h"
#define PADS_FUNCTION_SELECT0_ADDR (0xB8101C00 + 0xC0)
#define GPIO_BIT_EN_ADDR(bank) (0xB8101C00 + 0x200 + (0x24 * (bank)))
#define PAD_DRIVE_STRENGTH_ADDR(bank) (0xB8101C00 + 0x120 + (0x4 * (bank)))
#define MAX_NO_MFIOS 89
#define PAD_DRIVE_STRENGTH_LENGTH 2
#define PAD_DRIVE_STRENGTH_MASK 0x3
typedef enum {
DRIVE_STRENGTH_2mA = 0,
DRIVE_STRENGTH_4mA = 1,
DRIVE_STRENGTH_8mA = 2,
DRIVE_STRENGTH_12mA = 3
} drive_strength;
/* MFIO definitions for UART1 */
#define UART1_RXD_MFIO 59
#define UART1_TXD_MFIO 60
/* MFIO definitions for SPIM */
#define SPIM1_D0_TXD_MFIO 5
#define SPIM1_D1_RXD_MFIO 4
#define SPIM1_MCLK_MFIO 3
#define SPIM1_D2_MFIO 6
#define SPIM1_D3_MFIO 7
#define SPIM1_CS0_MFIO 0
/* MFIO definitions for I2C */
#define I2C_DATA_MFIO(i) (28 + (2*(i)))
#define I2C_CLK_MFIO(i) (29 + (2*(i)))
#define I2C_DATA_FUNCTION_OFFSET(i) (20 + (2*(i)))
#define I2C_CLK_FUNCTION_OFFSET(i) (21 + (2*(i)))
#define I2C_DATA_FUNCTION_MASK 0x1
#define I2C_CLK_FUNCTION_MASK 0x1
static void pad_drive_strength(u32 pad, drive_strength strength)
{
u32 reg, drive_strength_shift;
assert(pad <= MAX_NO_MFIOS);
assert(!(strength & ~(PAD_DRIVE_STRENGTH_MASK)));
/* Set drive strength value */
drive_strength_shift = (pad % 16) * PAD_DRIVE_STRENGTH_LENGTH;
reg = read32_x(PAD_DRIVE_STRENGTH_ADDR(pad / 16));
reg &= ~(PAD_DRIVE_STRENGTH_MASK << drive_strength_shift);
reg |= strength << drive_strength_shift;
write32_x(PAD_DRIVE_STRENGTH_ADDR(pad / 16), reg);
}
static void uart1_mfio_setup(void)
{
u32 reg, mfio_mask;
/*
* Disable GPIO for UART1 MFIOs
* All UART MFIOs have MFIO/16 = 3, therefore we use GPIO pad 3
* This is the only function (0) of these MFIOs and therfore there
* is no need to set up a function number in the corresponding
* function select register.
*/
reg = read32_x(GPIO_BIT_EN_ADDR(3));
mfio_mask = 1 << (UART1_RXD_MFIO % 16);
mfio_mask |= 1 << (UART1_TXD_MFIO % 16);
/* Clear relevant bits */
reg &= ~mfio_mask;
/*
* Set corresponding bits in the upper half word
* in order to be able to modify the chosen pins
*/
reg |= mfio_mask << 16;
write32_x(GPIO_BIT_EN_ADDR(3), reg);
}
static void spim1_mfio_setup(void)
{
u32 reg, mfio_mask;
/*
* Disable GPIO for SPIM1 MFIOs
* All SPFI1 MFIOs have MFIO/16 = 0, therefore we use GPIO pad 0
* This is the only function (0) of these MFIOs and therfore there
* is no need to set up a function number in the corresponding
* function select register.
*/
reg = read32_x(GPIO_BIT_EN_ADDR(0));
/* Disable GPIO for SPIM1 MFIOs */
mfio_mask = 1 << (SPIM1_D0_TXD_MFIO % 16);
mfio_mask |= 1 << (SPIM1_D1_RXD_MFIO % 16);
mfio_mask |= 1 << (SPIM1_MCLK_MFIO % 16);
mfio_mask |= 1 << (SPIM1_D2_MFIO % 16);
mfio_mask |= 1 << (SPIM1_D3_MFIO % 16);
mfio_mask |= 1 << (SPIM1_CS0_MFIO % 16);
/* Clear relevant bits */
reg &= ~mfio_mask;
/*
* Set corresponding bits in the upper half word
* in order to be able to modify the chosen pins
*/
reg |= mfio_mask << 16;
write32_x(GPIO_BIT_EN_ADDR(0), reg);
/* Set drive strength to maximum for these MFIOs */
pad_drive_strength(SPIM1_CS0_MFIO, DRIVE_STRENGTH_12mA);
pad_drive_strength(SPIM1_D1_RXD_MFIO, DRIVE_STRENGTH_12mA);
pad_drive_strength(SPIM1_D0_TXD_MFIO, DRIVE_STRENGTH_12mA);
pad_drive_strength(SPIM1_D2_MFIO, DRIVE_STRENGTH_12mA);
pad_drive_strength(SPIM1_D3_MFIO, DRIVE_STRENGTH_12mA);
pad_drive_strength(SPIM1_MCLK_MFIO, DRIVE_STRENGTH_12mA);
}
static void i2c_mfio_setup(int interface)
{
u32 reg, mfio_mask;
assert(interface < 4);
/*
* Disable GPIO for I2C MFIOs
*/
reg = read32_x(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16));
mfio_mask = 1 << (I2C_DATA_MFIO(interface) % 16);
mfio_mask |= 1 << (I2C_CLK_MFIO(interface) % 16);
/* Clear relevant bits */
reg &= ~mfio_mask;
/*
* Set corresponding bits in the upper half word
* in order to be able to modify the chosen pins
*/
reg |= mfio_mask << 16;
write32_x(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16), reg);
/* for I2C0 and I2C1:
* Set bits to 0 (clear) which is the primary function
* for these MFIOs; those bits will all be set to 1 by
* default.
* There is no need to do that for I2C2 and I2C3
*/
if (interface > 1)
return;
reg = read32_x(PADS_FUNCTION_SELECT0_ADDR);
reg &= ~(I2C_DATA_FUNCTION_MASK <<
I2C_DATA_FUNCTION_OFFSET(interface));
reg &= ~(I2C_CLK_FUNCTION_MASK <<
I2C_CLK_FUNCTION_OFFSET(interface));
write32_x(PADS_FUNCTION_SELECT0_ADDR, reg);
}
static void bootblock_mainboard_init(void)
{
int ret;
/* System PLL divided by 2 -> 350 MHz */
/* The same frequency will be the input frequency for the SPFI block */
system_clk_setup(1);
/* MIPS CPU dividers: division by 1 -> 546 MHz
* This is set up as we cannot make any assumption about
* the values set or not by the boot ROM code */
mips_clk_setup(0, 0);
/* Setup system PLL at 700 MHz */
ret = sys_pll_setup(2, 1, 13, 350);
if (ret != CLOCKS_OK)
return;
/* Setup MIPS PLL at 546 MHz */
ret = mips_pll_setup(2, 1, 1, 21);
if (ret != CLOCKS_OK)
return;
/*
* Move peripheral clock control from RPU to MIPS.
* The RPU gate register is not managed in Linux so disable its default
* values and assign MIPS gate register the default values.
* *Note*: All unused clocks will be gated by Linux
*/
setup_clk_gate_defaults();
/* Setup SPIM1 MFIOs */
spim1_mfio_setup();
/* Setup UART1 clock and MFIOs
* System PLL divided by 5 divided by 76 -> 1.8421 Mhz
*/
uart1_clk_setup(4, 75);
uart1_mfio_setup();
}
static int init_extra_hardware(void)
{
const struct board_hw *hardware;
/* Obtain information about current board */
hardware = board_get_hw();
if (!hardware) {
printk(BIOS_ERR, "%s: Invalid hardware information.\n",
__func__);
return -1;
}
/* Setup USB clock
* System clock divided by 7 -> 50 MHz
*/
if (usb_clk_setup(6, 2, 7) != CLOCKS_OK) {
printk(BIOS_ERR, "%s: Failed to set up USB clock.\n",
__func__);
return -1;
}
/* Setup I2C clocks and MFIOs
* System clock divided by 4 divided by 3 -> 29.1(6) MHz
*/
i2c_clk_setup(3, 2, hardware->i2c_interface);
i2c_mfio_setup(hardware->i2c_interface);
/* Ethernet clocks setup: ENET as clock source */
eth_clk_setup(0, 6);
/* ROM clock setup: system clock divided by 2 -> 175 MHz */
/* Hash accelerator is driven from the ROM clock */
rom_clk_setup(1);
return 0;
}

36
src/mainboard/google/urara/chromeos.c
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <boot/coreboot_tables.h>
#include <bootmode.h>
#include <console/console.h>
#include <gpio.h>
int get_write_protect_state(void)
{
printk(BIOS_ERR, "%s unsupported, but called\n", __func__);
return 0;
}
void fill_lb_gpios(struct lb_gpios *gpios)
{
printk(BIOS_ERR, "%s unsupported, but called\n", __func__);
}
int get_recovery_mode_switch(void)
{
printk(BIOS_ERR, "%s unsupported, but called\n", __func__);
return 0;
}

32
src/mainboard/google/urara/chromeos.fmd
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FLASH@0x0 0x200000 {
WP_RO@0x0 0x100000 {
RO_SECTION@0x0 0xf0000 {
BOOTBLOCK@0 128K
COREBOOT(CBFS)@0x20000 0x60000
FMAP@0xe0000 0x1000
GBB@0xe1000 0xef00
RO_FRID@0xeff00 0x100
}
RO_VPD(PRESERVE)@0xf0000 0x10000
}
RW_SECTION_A@0x100000 0x70000 {
VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x2000 0x6df00
RW_FWID_A@0x6ff00 0x100
}
RW_SHARED@0x170000 0x2000 {
SHARED_DATA@0x0 0x2000
}
RW_GPT@0x172000 0x2000 {
RW_GPT_PRIMARY@0x0 0x1000
RW_GPT_SECONDARY@0x1000 0x1000
}
RW_ELOG(PRESERVE)@0x174000 0x4000
RW_VPD(PRESERVE)@0x178000 0x8000
RW_SECTION_B@0x180000 0x70000 {
VBLOCK_B@0x0 0x2000
FW_MAIN_B(CBFS)@0x2000 0x6df00
RW_FWID_B@0x6ff00 0x100
}
RW_NVRAM(PRESERVE)@0x1f0000 0x10000
}

22
src/mainboard/google/urara/devicetree.cb
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2014 Imagination Technologies
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
chip soc/imgtec/pistachio
device cpu_cluster 0 on end
chip drivers/generic/generic # I2C0 controller
device i2c 6 on end # Fake component for testing
end
end

55
src/mainboard/google/urara/mainboard.c
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <symbols.h>
#include <console/console.h>
#include <device/device.h>
#include <boot/coreboot_tables.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_init(struct device *dev)
{
#if CONFIG(CHROMEOS)
/* Copy WIFI calibration data into CBMEM. */
cbmem_add_vpd_calibration_data();
#endif
}
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Enable Pistachio device...\n");
dev->ops->init = &mainboard_init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
void lb_board(struct lb_header *header)
{
struct lb_range *dma;
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAG_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = REGION_SIZE(dma_coherent);
#if CONFIG(CHROMEOS)
/* Retrieve the switch interface MAC addresses. */
lb_table_add_macs_from_vpd(header);
#endif
}

16
src/mainboard/google/urara/memlayout.ld
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@ -1,16 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/memlayout.ld>

38
src/mainboard/google/urara/urara_boardid.h
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@ -1,38 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__
#define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__
#include <stdint.h>
/*
* List of URARA derivatives board ID definitions. They are stored in uint8_t
* across the code, using #defines here not to imply any specific size.
*/
#define URARA_BOARD_ID_BUB 0
#define URARA_BOARD_ID_BURANKU 1
#define URARA_BOARD_ID_DERWENT 2
#define URARA_BOARD_ID_JAGUAR 3
#define URARA_BOARD_ID_KENNET 4
#define URARA_BOARD_ID_SPACE 5
struct board_hw {
uint8_t i2c_interface;
};
const struct board_hw *board_get_hw(void);
#endif