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Remove DEFAULT_PCIEXBAR alias 

The other DEFAULT_ entries are just immediate
constants.

Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2019-03-05 07:54:28 +02:00 committed by Nico Huber
parent e079e5ccc2
commit 503d3247e4
26 changed files with 23 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/include/device/pci_mmio_cfg.h
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@ -20,13 +20,12 @@
#include <device/mmio.h>
#include <device/pci_type.h>
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
static __always_inline
u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where);
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | where);
return read8(addr);
}
@ -34,7 +33,7 @@ static __always_inline
u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1));
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1));
return read16(addr);
}
@ -42,7 +41,7 @@ static __always_inline
u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3));
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3));
return read32(addr);
}
@ -50,7 +49,7 @@ static __always_inline
void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where);
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | where);
write8(addr, value);
}
@ -58,7 +57,7 @@ static __always_inline
void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1));
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1));
write16(addr, value);
}
@ -66,7 +65,7 @@ static __always_inline
void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3));
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3));
write32(addr, value);
}

2
src/mainboard/asrock/h81m-hds/romstage.c
View File

@ -77,7 +77,7 @@ void mainboard_romstage_entry(unsigned long bist)
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/google/beltino/romstage.c
View File

@ -75,7 +75,7 @@ void mainboard_romstage_entry(unsigned long bist)
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/google/slippy/variants/falco/romstage.c
View File

@ -112,7 +112,7 @@ void variant_romstage_entry(unsigned long bist)
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/google/slippy/variants/leon/romstage.c
View File

@ -109,7 +109,7 @@ void variant_romstage_entry(unsigned long bist)
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/google/slippy/variants/peppy/romstage.c
View File

@ -127,7 +127,7 @@ void variant_romstage_entry(unsigned long bist)
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/google/slippy/variants/wolf/romstage.c
View File

@ -114,7 +114,7 @@ void variant_romstage_entry(unsigned long bist)
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/intel/baskingridge/romstage.c
View File

@ -70,7 +70,7 @@ void mainboard_romstage_entry(unsigned long bist)
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/supermicro/x10slm-f/romstage.c
View File

@ -69,7 +69,7 @@ void mainboard_romstage_entry(unsigned long bist)
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/northbridge/intel/gm45/acpi/gm45.asl
View File

@ -40,7 +40,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

2
src/northbridge/intel/gm45/gm45.h
View File

@ -195,8 +195,6 @@ enum {
#define DEFAULT_EPBAR 0xfed19000
#define DEFAULT_HECIBAR ((u8 *)0xfed1a000)
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
#define IOMMU_BASE1 0xfed90000
#define IOMMU_BASE2 0xfed91000

2
src/northbridge/intel/haswell/acpi/haswell.asl
View File

@ -28,7 +28,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

1
src/northbridge/intel/haswell/haswell.h
View File

@ -26,7 +26,6 @@
#define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#ifndef __ACPI__
#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */

2
src/northbridge/intel/i945/acpi/i945.asl
View File

@ -55,7 +55,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

1
src/northbridge/intel/i945/i945.h
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@ -17,7 +17,6 @@
#define NORTHBRIDGE_INTEL_I945_H
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_X60BAR 0xfed13000
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */

2
src/northbridge/intel/nehalem/acpi/nehalem.asl
View File

@ -28,7 +28,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

2
src/northbridge/intel/nehalem/bootblock.c
View File

@ -15,6 +15,6 @@
static void bootblock_northbridge_init(void)
{
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, DEFAULT_PCIEXBAR | 1);
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1);
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0);
}

3
src/northbridge/intel/nehalem/nehalem.h
View File

@ -52,8 +52,6 @@ typedef struct {
#define DEFAULT_HECIBAR ((u8 *)0xfed17000)
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
#define IOMMU_BASE1 0xfed90000
#define IOMMU_BASE2 0xfed91000
@ -128,7 +126,6 @@ typedef struct {
#define IED_SIZE 0x400000
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */

2
src/northbridge/intel/pineview/acpi/pineview.asl
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@ -33,7 +33,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x10000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */

3
src/northbridge/intel/pineview/iomap.h
View File

@ -17,9 +17,6 @@
#ifndef PINEVIEW_IOMAP_H
#define PINEVIEW_IOMAP_H
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */

2
src/northbridge/intel/sandybridge/acpi/sandybridge.asl
View File

@ -30,7 +30,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

1
src/northbridge/intel/sandybridge/sandybridge.h
View File

@ -39,7 +39,6 @@
#define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */

2
src/northbridge/intel/x4x/acpi/x4x.asl
View File

@ -29,7 +29,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

3
src/northbridge/intel/x4x/iomap.h
View File

@ -17,9 +17,6 @@
#ifndef X4X_IOMAP_H
#define X4X_IOMAP_H
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */

2
src/soc/intel/denverton_ns/acpi/northcluster.asl
View File

@ -138,7 +138,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
// PCIEXBAR memory range
Memory32Fixed(ReadOnly, DEFAULT_PCIEXBAR, 0x10000000)
Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000)
// TSEG
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB)
})

1
src/soc/intel/denverton_ns/include/soc/iomap.h
View File

@ -23,7 +23,6 @@
*/
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
/* Southbridge internal device IO BARs (Set to match FSP settings) */