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arch/arm/armv7: Correct checkpatch errors

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- Correct whitespace issues with files under arch/arm/armv7.
- Fix comments and remove unnecessary line continuations in mmu.c

Change-Id: I69d50030b07b1919555feca44967472922176a81
Signed-off-by: Logan Carlson <logancarlson@google.com>
Reviewed-on: https://review.coreboot.org/19996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Logan Carlson 2017-05-31 12:01:01 -06:00 committed by Martin Roth
parent 80358a1f47
commit 50522254fb
3 changed files with 7 additions and 7 deletions
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2
src/arch/arm/armv7/cache.c
View file

@ -84,7 +84,7 @@ static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op)
dsb(); dsb();
while ((void *)line < addr + len) { while ((void *)line < addr + len) {
switch(op) { switch (op) {
case OP_DCCIMVAC: case OP_DCCIMVAC:
dccimvac(line); dccimvac(line);
break; break;

10
src/arch/arm/armv7/mmu.c
View file

@ -46,10 +46,10 @@
0ULL << 54 | /* XN. 0:Not restricted */ \ 0ULL << 54 | /* XN. 0:Not restricted */ \
0ULL << 53 | /* PXN. 0:Not restricted */ \ 0ULL << 53 | /* PXN. 0:Not restricted */ \
1 << 10 | /* AF. 1:Accessed. This is to prevent access \ 1 << 10 | /* AF. 1:Accessed. This is to prevent access \
* fault when accessed for the first time */ \ * fault when accessed for the first time */ \
0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \ 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \
0 << 5 | /* NS. 0:Output address is in Secure space */ \ 0 << 5 | /* NS. 0:Output address is in Secure space */ \
0 << 1 | /* block/table. 0:block entry */ \ 0 << 1 | /* block/table. 0:block entry */ \
1 << 0 /* validity. 1:valid */ \ 1 << 0 /* validity. 1:valid */ \
) )
#define ATTR_PAGE (ATTR_BLOCK | 1 << 1) #define ATTR_PAGE (ATTR_BLOCK | 1 << 1)
@ -280,12 +280,12 @@ void mmu_init(void)
table[0] = ATTR_UNUSED; table[0] = ATTR_UNUSED;
if (CONFIG_ARM_LPAE) { if (CONFIG_ARM_LPAE) {
pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB); pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB);
pte_t *pmd = ttb_buff; pte_t *pmd = ttb_buff;
int i; int i;
printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n", printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
ttb_buff); ttb_buff);
ASSERT((read_mmfr0() & 0xf) >= 5); ASSERT((read_mmfr0() & 0xf) >= 5);
/* /*
@ -308,7 +308,7 @@ void mmu_init(void)
*/ */
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) | pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |
ATTR_NEXTLEVEL; ATTR_NEXTLEVEL;
pmd += BLOCK_SIZE / PAGE_SIZE; pmd += BLOCK_SIZE / PAGE_SIZE;
} }

2
src/arch/arm/armv7/thread.c
View file

@ -39,7 +39,7 @@ static inline uintptr_t push_stack(uintptr_t cur_stack, uintptr_t value)
} }
void arch_prepare_thread(struct thread *t, void arch_prepare_thread(struct thread *t,
void asmlinkage (*thread_entry)(void *), void *arg) void asmlinkage(*thread_entry)(void *), void *arg)
{ {
uintptr_t stack = t->stack_current; uintptr_t stack = t->stack_current;
int i; int i;