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mainboard/google/zoombini: add EC to ACPI tables 

this adds missing ACPI entries for the EC, CPU, and power button.
also, the EC to AP wakeup pin assignment is fixed.

BUG=b:71819257
BRANCH=chromeos-2016.05
TEST=booted on meowth.  /sys/class/power_supply now gets populated.

Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/23237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
Caveh Jalali 2018-01-11 20:12:39 -08:00 committed by Shelley Chen
parent 7ea8e02f4b
commit 50657aa48e
2 changed files with 20 additions and 1 deletions
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19
src/mainboard/google/zoombini/dsdt.asl
View File

@ -15,6 +15,9 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "variant/ec.h"
#include "variant/gpio.h"
DefinitionBlock( DefinitionBlock(
"dsdt.aml", "dsdt.aml",
"DSDT", "DSDT",
@ -30,7 +33,14 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <soc/intel/cannonlake/acpi/globalnvs.asl> #include <soc/intel/cannonlake/acpi/globalnvs.asl>
// CPU
#include <soc/intel/cannonlake/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
}
Device (PCI0) Device (PCI0)
{ {
#include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/northbridge.asl>
@ -45,4 +55,13 @@ DefinitionBlock(
// Chipset specific sleep states // Chipset specific sleep states
#include <soc/intel/cannonlake/acpi/sleepstates.asl> #include <soc/intel/cannonlake/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
} }

2
src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
View File

@ -32,7 +32,7 @@
#define GPIO_PCH_WP GPP_A1 #define GPIO_PCH_WP GPP_A1
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPP_74 #define GPE_EC_WAKE GPE0_LAN_WAK
/* eSPI virtual wire reporting */ /* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI #define EC_SCI_GPI GPE0_ESPI