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mb/google/nissa/var/quandiso: Add LTE only daughterboard support 

Quandiso does not use DB_1C, replace the fw_config with LTE only
daughterboard.

BUG=b:312094048
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Robert Chen 2023-11-28 02:24:58 -05:00 committed by Felix Held
parent 22ac6f6b2c
commit 508296333b
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/brya/variants/quandiso/fw_config.c
View File

@ -75,7 +75,8 @@ static const struct pad_config disable_wifi_pch_susclk[] = {
void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
{
if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) &&
!fw_config_probe(FW_CONFIG(DB_USB, DB_LTE))) {
printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n");
gpio_padbased_override(padbased_table, lte_disable_pads,
ARRAY_SIZE(lte_disable_pads));

7
src/mainboard/google/brya/variants/quandiso/overridetree.cb
View File

@ -2,7 +2,7 @@ fw_config
field DB_USB 0 1
option DB_NONE 0
option DB_1C_1A 1
option DB_1C 2
option DB_LTE 2
option DB_1C_LTE 3
end
field WIFI_SAR_ID 2 3
@ -333,6 +333,7 @@ chip soc/intel/alderlake
register "reg_adv_ctrl19" = "0xf0"
register "reg_adv_ctrl20" = "0xf0"
device i2c 28 on
probe DB_USB DB_LTE
probe DB_USB DB_1C_LTE
end
end
@ -444,7 +445,6 @@ chip soc/intel/alderlake
use tcss_usb3_port2 as usb3_port
device generic 1 alias conn1 on
probe DB_USB DB_1C_1A
probe DB_USB DB_1C
probe DB_USB DB_1C_LTE
end
end
@ -468,7 +468,6 @@ chip soc/intel/alderlake
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port2 on
probe DB_USB DB_1C_1A
probe DB_USB DB_1C
probe DB_USB DB_1C_LTE
end
end
@ -492,7 +491,6 @@ chip soc/intel/alderlake
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port2 on
probe DB_USB DB_1C_1A
probe DB_USB DB_1C
probe DB_USB DB_1C_LTE
end
end
@ -565,6 +563,7 @@ chip soc/intel/alderlake
register "desc" = ""USB3 WWAN""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb3_port2 on
probe DB_USB DB_LTE
probe DB_USB DB_1C_LTE
end
end