src/mainboard to src/security: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Martin Roth
Martin Roth
parent
0949e73906
commit
50863daef8
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@ -127,7 +127,7 @@ chip soc/amd/picasso
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.flash_ch_en = 0,
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}"
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# genral purpose PCIe clock output configuration
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# general purpose PCIe clock output configuration
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register "gpp_clk_config[0]" = "GPP_CLK_OFF"
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register "gpp_clk_config[1]" = "GPP_CLK_OFF"
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register "gpp_clk_config[2]" = "GPP_CLK_REQ"
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@ -118,7 +118,7 @@ chip soc/amd/picasso
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.flash_ch_en = 0,
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}"
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# genral purpose PCIe clock output configuration
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# general purpose PCIe clock output configuration
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register "gpp_clk_config[0]" = "GPP_CLK_REQ"
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register "gpp_clk_config[1]" = "GPP_CLK_REQ"
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register "gpp_clk_config[2]" = "GPP_CLK_REQ"
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@ -118,7 +118,7 @@ chip soc/amd/picasso
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.flash_ch_en = 0,
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}"
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# genral purpose PCIe clock output configuration
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# general purpose PCIe clock output configuration
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register "gpp_clk_config[0]" = "GPP_CLK_REQ"
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register "gpp_clk_config[1]" = "GPP_CLK_REQ"
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register "gpp_clk_config[2]" = "GPP_CLK_REQ"
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@ -129,7 +129,7 @@ chip northbridge/intel/sandybridge
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irq 0xe9 = 0x02
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irq 0xf0 = 0x20
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end
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device pnp 2e.b off end # HWM, front pannel LED
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device pnp 2e.b off end # HWM, front panel LED
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device pnp 2e.d on end # VID
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device pnp 2e.e off end # CIR WAKE-UP
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device pnp 2e.f on end # GPIO Push-Pull or Open-drain
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@ -105,7 +105,7 @@ chip northbridge/intel/x4x # Northbridge
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irq 0xe9 = 0x02
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irq 0xf0 = 0x20
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end
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device pnp 2e.b on # HWM, front pannel LED
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device pnp 2e.b on # HWM, front panel LED
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io 0x60 = 0x290
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io 0x62 = 0x200
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irq 0x70 = 0
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@ -99,7 +99,7 @@ chip northbridge/intel/x4x # Northbridge
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device pnp 2e.a on # ACPI
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irq 0xe4 = 0x10 # Power dram during s3
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end
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device pnp 2e.b on # HWM, front pannel LED
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device pnp 2e.b on # HWM, front panel LED
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io 0x60 = 0x290
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irq 0x70 = 0
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end
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@ -100,7 +100,7 @@ chip northbridge/intel/x4x # Northbridge
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device pnp 2e.a on # ACPI
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irq 0xe4 = 0x10 # Power dram during s3
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end
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device pnp 2e.b on # HWM, front pannel LED
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device pnp 2e.b on # HWM, front panel LED
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io 0x60 = 0x290
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irq 0x70 = 0
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end
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@ -34,7 +34,7 @@ chip northbridge/intel/x4x # Northbridge
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irq 0x70 = 0
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irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
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end
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device pnp 2e.b on # HWM, front pannel LED
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device pnp 2e.b on # HWM, front panel LED
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io 0x60 = 0x290
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irq 0x70 = 0
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end
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@ -106,9 +106,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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{ 1, 0, 0x0080 }, /* USB3 front internal header */
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{ 1, 0, 0x0080 }, /* USB3 front internal header */
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{ 1, 1, 0x0080 }, /* USB3 ETH top connector */
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{ 1, 1, 0x0080 }, /* USB3 ETH botton connector */
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{ 1, 1, 0x0080 }, /* USB3 ETH bottom connector */
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{ 1, 2, 0x0080 }, /* USB2 PS2 top connector */
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{ 1, 2, 0x0080 }, /* USB2 PS2 botton connector */
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{ 1, 2, 0x0080 }, /* USB2 PS2 bottom connector */
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{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
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{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
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{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
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@ -18,7 +18,7 @@
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* with -bios option which neatly puts coreboot into flash and so payloads
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* can find CBFS and we don't risk overwriting CBFS.
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*
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* Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash
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* Prior to Jul 2014 qemu aliased 0 to beginning of RAM instead of flash
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* and -bios was unusable as $pc pointed to 0 which was zero-filled as a
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* workaround we suggested using -kernel but this still had all the issues
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* of having fake-ROM in RAM. In fact it was even worse as fake ROM ends
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@ -2,7 +2,7 @@
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/*
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* These are the qemu firmware config interface defines and structs.
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* Copied over from qemu soure tree,
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* Copied over from qemu source tree,
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* include/standard-headers/linux/qemu_fw_cfg.h and modified accordingly.
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*/
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#ifndef FW_CFG_IF_H
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@ -16,7 +16,7 @@ static void bootblock_northbridge_init(void)
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final
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* assumption is that no assembly code is using the
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* CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
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* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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@ -181,7 +181,7 @@ static const struct edp_data b101uan08_table[] = {
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{6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00} },
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{6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} },
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{6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} },
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/* Additional Settng for eDP */
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/* Additional Setting for eDP */
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{3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} },
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{3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} },
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/* DPRX CAD Register Setting */
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@ -39,7 +39,7 @@
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# 4 SDRAM CHIP Density and Banks
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# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
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# bits[6:4]: 0 = 3 (8 banks)
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# bits[7]: reserverd
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# bits[7]: reserved
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05
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# 5 SDRAM Addressing
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@ -39,7 +39,7 @@
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# 4 SDRAM CHIP Density and Banks
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# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
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# bits[6:4]: 0 = 3 (8 banks)
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# bits[7]: reserverd
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# bits[7]: reserved
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05
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# 5 SDRAM Addressing
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@ -38,7 +38,7 @@
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# 4 SDRAM CHIP Density and Banks
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# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
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# bits[6:4]: 0 = 3 (8 banks)
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# bits[7]: reserverd
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# bits[7]: reserved
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04
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# 5 SDRAM Addressing
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@ -202,7 +202,7 @@ static void setup_storage(void)
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static void gpio_init(void)
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{
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/* Set up the I2C busses. */
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/* Set up the I2C buses. */
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exynos_pinmux_i2c0();
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exynos_pinmux_i2c1();
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exynos_pinmux_i2c2();
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@ -222,7 +222,7 @@ static void gpio_init(void)
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gpio_direction_output(GPIO_X17, 1);
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gpio_direction_output(GPIO_X15, 1);
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/* Set up the I2S busses. */
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/* Set up the I2S buses. */
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exynos_pinmux_i2s0();
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exynos_pinmux_i2s1();
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}
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@ -1,5 +1,5 @@
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#
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# Set DebugCtrl to 1 to reenable Jtag
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# Set DebugCtrl to 1 to re-enable Jtag
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#
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DebugCtrl = 0;
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#
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@ -60,7 +60,7 @@ int pwm_enum_to_pwm_number[] = {
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void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt)
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{
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int duty_ns, voltage_max, voltage_min;
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int voltage = millivolt * 10; /* for higer calculation accuracy */
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int voltage = millivolt * 10; /* for higher calculation accuracy */
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int pwm_number = pwm_enum_to_pwm_number[pwm];
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voltage_min = pwm_design_voltage[pwm][0];
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@ -80,7 +80,7 @@ chip soc/amd/cezanne
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register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR
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register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC
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# genral purpose PCIe clock output configuration
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# general purpose PCIe clock output configuration
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register "gpp_clk_config[0]" = "GPP_CLK_REQ"
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register "gpp_clk_config[1]" = "GPP_CLK_REQ"
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register "gpp_clk_config[2]" = "GPP_CLK_REQ"
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@ -44,7 +44,7 @@ chip soc/intel/cannonlake
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register "tcc_offset" = "10" # TCC of 90C
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# Unlock GPIO pads
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register "PchUnlockGpioPads" = "1"
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# SD card WP pin confguration
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# SD card WP pin configuration
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register "ScsSdCardWpPinEnabled" = "0"
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# NOTE: if any variant wants to override this value, use the same format
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@ -117,7 +117,7 @@ static void mainboard_init(void *chip_info)
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gpios = variant_gpio_table(&num_gpios);
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gpio_configure_pads(gpios, num_gpios);
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/* Initialize i2c busses that were not initialized in bootblock */
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/* Initialize i2c buses that were not initialized in bootblock */
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i2c_soc_init();
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/* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */
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@ -7,7 +7,7 @@ static void prepare_usb(void)
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{
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/*
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* Do DWC3 core and phy reset. Kick these resets off early
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* so they get atleast 1msec to settle.
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* so they get at least 1msec to settle.
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*/
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reset_usb(HSUSB_HS_PORT_1);
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}
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@ -231,7 +231,7 @@ static void display_startup(void)
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static void mainboard_init(struct device *dev)
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{
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/* TP_SHIFT_EN: Enables the level shifter for I2C bus 4 (TPAD), which
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* also contains the PS8640 eDP brige and the USB hub.
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* also contains the PS8640 eDP bridge and the USB hub.
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*/
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if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5)
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mt6391_gpio_output(MT6391_KP_ROW2, 1);
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@ -69,7 +69,7 @@ static void gpio_modification_by_ssfc(struct pad_config *table, size_t num)
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/*
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* Currently we only have the case of RT5682 as the second source. And
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* in case of Ampton which used RT5682 as the default source, it didn't
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* provide override_table right now so it will be returned ealier since
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* provide override_table right now so it will be returned earlier since
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* table above is NULL.
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*/
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if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682)
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@ -324,7 +324,7 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
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/*
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* ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak
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* ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak
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* pull-up for proper operation. Since there is no external pull present
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* on this platform, configure an internal weak pull-up.
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*/
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@ -25,7 +25,7 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
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/*
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* ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak
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* ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak
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* pull-up for proper operation. Since there is no external pull present
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* on this platform, configure an internal weak pull-up.
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*/
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@ -330,7 +330,7 @@ static void setup_storage(void)
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static void gpio_init(void)
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{
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/* Set up the I2C busses. */
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/* Set up the I2C buses. */
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exynos_pinmux_i2c2();
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exynos_pinmux_i2c4();
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exynos_pinmux_i2c7();
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@ -262,7 +262,7 @@ Scope (\_SB.PCI0.I2C2)
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* AX1V: Auxiliary LDO1 VR voltage value
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* AX2V: Auxiliary LDO2 VR voltage value
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* ACVA: Analog LDO VR voltage
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* DCVA: Core buck VR volatage
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* DCVA: Core buck VR voltage
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*/
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OperationRegion (PWR2, 0xB1, Zero, 0x0100)
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Field (PWR2, DWordAcc, NoLock, Preserve)
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@ -1,5 +1,5 @@
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#
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# Set JtagCtrl to 1 to reenable Jtag
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# Set JtagCtrl to 1 to re-enable Jtag
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#
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JtagCtrl = 0;
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#
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@ -17,7 +17,7 @@ DefinitionBlock(
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#include "acpi/platform.asl"
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#include "acpi/mainboard.asl"
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// Thermal handeler
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// Thermal handler
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#include "acpi/thermal.asl"
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// global NVS and variables
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@ -21,7 +21,7 @@ chip soc/amd/picasso
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}"
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# Start : OPN Performance Configuration
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# (Configuratin that is common for all variants)
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# (Configuration that is common for all variants)
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# For the below fields, 0 indicates use SOC default
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# PROCHOT_L de-assertion Ramp Time
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@ -232,7 +232,7 @@ chip soc/amd/picasso
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register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
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# genral purpose PCIe clock output configuration
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# general purpose PCIe clock output configuration
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register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
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register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
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register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD
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@ -19,7 +19,7 @@ chip soc/amd/picasso
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}"
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# Start : OPN Performance Configuration
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# (Configuratin that is common for all variants)
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# (Configuration that is common for all variants)
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# For the below fields, 0 indicates use SOC default
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# PROCHOT_L de-assertion Ramp Time
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@ -230,7 +230,7 @@ chip soc/amd/picasso
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register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
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# genral purpose PCIe clock output configuration
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# general purpose PCIe clock output configuration
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register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
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register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
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register "gpp_clk_config[2]" = "GPP_CLK_OFF"
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@ -49,7 +49,7 @@ void variant_touchscreen_update(void);
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void variant_pcie_gpio_configure(void);
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/* Per variant FSP-S initialization, default implementation in baseboard and
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* overrideable by the variant. */
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* overridable by the variant. */
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void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs,
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size_t *dxio_num,
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const fsp_ddi_descriptor **ddi_descs,
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@ -81,7 +81,7 @@ chip northbridge/intel/sandybridge
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device pnp 4e.609 off end # GPIO6
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device pnp 4e.709 off end # GPIO7
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device pnp 4e.a on end # ACPI
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device pnp 4e.b on # HWM, front pannel LED
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device pnp 4e.b on # HWM, front panel LED
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io 0x60 = 0xa30
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io 0x62 = 0 # unused
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end
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@ -129,7 +129,7 @@ chip northbridge/intel/x4x # Northbridge
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irq 0xe4 = 0x10 # Power dram during s3
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irq 0xe6 = 0x8c
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end
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device pnp 2e.b on # HWM, front pannel LED
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device pnp 2e.b on # HWM, front panel LED
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io 0x60 = 0xa00
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irq 0x70 = 0
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end
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@ -108,7 +108,7 @@ Scope (\_SB.PCI0.I2C2)
|
|||
* AX1V: Auxiliary LDO1 VR voltage value
|
||||
* AX2V: Auxiliary LDO2 VR voltage value
|
||||
* ACVA: Analog LDO VR voltage
|
||||
* DCVA: Core buck VR volatage
|
||||
* DCVA: Core buck VR voltage
|
||||
*/
|
||||
OperationRegion (PWR2, 0xB1, Zero, 0x0100)
|
||||
Field (PWR2, DWordAcc, NoLock, Preserve)
|
||||
|
|
@ -613,7 +613,7 @@ Scope (\_SB.PCI0.I2C3)
|
|||
* AX1V: Auxiliary LDO1 VR voltage value
|
||||
* AX2V: Auxiliary LDO2 VR voltage value
|
||||
* ACVA: Analog LDO VR voltage
|
||||
* DCVA: Core buck VR volatage
|
||||
* DCVA: Core buck VR voltage
|
||||
*/
|
||||
OperationRegion (PWR2, 0xB1, Zero, 0x0100)
|
||||
Field (PWR2, DWordAcc, NoLock, Preserve)
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Customer Overides Memory Table
|
||||
* @brief Customer Overrides Memory Table
|
||||
*
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform
|
||||
* information to AGESA
|
||||
|
|
|
|||
|
|
@ -144,7 +144,7 @@ Device (EC0)
|
|||
^HKEY.MHKQ (0x6040)
|
||||
}
|
||||
|
||||
/* Lid openend */
|
||||
/* Lid opened */
|
||||
Method (_Q2A, 0, NotSerialized)
|
||||
{
|
||||
LIDS = 1
|
||||
|
|
|
|||
|
|
@ -535,7 +535,7 @@ DefinitionBlock (
|
|||
* The Secondary bus range for PCI0 lets the system
|
||||
* know what bus values are allowed on the downstream
|
||||
* side of this PCI bus if there is a PCI-PCI bridge.
|
||||
* PCI busses can have 256 secondary busses which
|
||||
* PCI buses can have 256 secondary buses which
|
||||
* range from [0-0xFF] but they do not need to be
|
||||
* sequential.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
# 4 SDRAM CHIP Density and Banks
|
||||
# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
|
||||
# bits[6:4]: 0 = 3 (8 banks)
|
||||
# bits[7]: reserverd
|
||||
# bits[7]: reserved
|
||||
05
|
||||
|
||||
# 5 SDRAM Addressing
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
# 4 SDRAM CHIP Density and Banks
|
||||
# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
|
||||
# bits[6:4]: 0 = 3 (8 banks)
|
||||
# bits[7]: reserverd
|
||||
# bits[7]: reserved
|
||||
05
|
||||
|
||||
# 5 SDRAM Addressing
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
# 4 SDRAM CHIP Density and Banks
|
||||
# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
|
||||
# bits[6:4]: 0 = 3 (8 banks)
|
||||
# bits[7]: reserverd
|
||||
# bits[7]: reserved
|
||||
04
|
||||
|
||||
# 5 SDRAM Addressing
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
void mainboard_after_memory_init(void)
|
||||
{
|
||||
/*
|
||||
* FSP enables internal UART. Disable it and reenable Super I/O UART to
|
||||
* FSP enables internal UART. Disable it and re-enable Super I/O UART to
|
||||
* prevent loss of debug information on serial.
|
||||
*/
|
||||
pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0);
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ Device (EC)
|
|||
BIF0, 16,
|
||||
BDCP, 16, // BAT Design Capacity
|
||||
BFCP, 16, // BAT Full Capacity
|
||||
BRCH, 16, // BAT Rechargable
|
||||
BRCH, 16, // BAT Rechargeable
|
||||
BDVT, 16, // BAT Design Voltage
|
||||
BIF5, 16,
|
||||
BIF6, 16,
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ Device(EC0)
|
|||
FDDI, 1, // floppy on lpt indicator?
|
||||
LIDC, 1, // LID switch
|
||||
Offset(0xd0),
|
||||
TCPU, 8, // T_CPU in deg Celcius
|
||||
TCPU, 8, // T_CPU in deg Celsius
|
||||
Offset(0xd6),
|
||||
/* exact purpose of these three is guessed,
|
||||
but it's something about cooling */
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
Scope (\_TZ)
|
||||
{
|
||||
/* degree Celcius to deci-Kelvin (ACPI temperature unit) */
|
||||
/* degree Celsius to deci-Kelvin (ACPI temperature unit) */
|
||||
Method(C2dK, 1) {
|
||||
Add (2732, Multiply (Arg0, 10), Local0)
|
||||
Return (Local0)
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ static const char *northbridge_acpi_name(const struct device *dev)
|
|||
}
|
||||
|
||||
/*
|
||||
* TODO: We could determine how many PCIe busses we need in the bar.
|
||||
* TODO: We could determine how many PCIe buses we need in the bar.
|
||||
* For now, that number is hardcoded to a max of 64.
|
||||
*/
|
||||
static struct device_operations pci_domain_ops = {
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ config MAXIMUM_SUPPORTED_FREQUENCY
|
|||
config CHECK_SLFRCS_ON_RESUME
|
||||
def_bool n
|
||||
help
|
||||
On some boards it may be neccessary to hard reset early
|
||||
On some boards it may be necessary to hard reset early
|
||||
during resume from S3 if the SLFRCS register indicates that
|
||||
a memory channel is not guaranteed to be in self-refresh.
|
||||
On other boards the check always creates a false positive,
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ void bootblock_early_northbridge_init(void)
|
|||
{
|
||||
/*
|
||||
* The QuickPath bus number is the topmost bus number, as per the value
|
||||
* of the SAD_PCIEXBAR register. The register defaults to 256 busses on
|
||||
* of the SAD_PCIEXBAR register. The register defaults to 256 buses on
|
||||
* reset. Thus, hardcode the bus number when first setting up PCIEXBAR.
|
||||
*/
|
||||
const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1);
|
||||
|
|
|
|||
|
|
@ -2437,7 +2437,7 @@ int aggressive_write_training(ramctr_timing *ctrl)
|
|||
if (enable_iosav_opt)
|
||||
mchbar_write32(MCMNTS_SPARE, 1);
|
||||
|
||||
printram("Aggresive write training:\n");
|
||||
printram("Aggressive write training:\n");
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) {
|
||||
FOR_ALL_POPULATED_CHANNELS {
|
||||
|
|
|
|||
|
|
@ -123,7 +123,7 @@ void intel_cbnt_log_registers(void)
|
|||
LOG("SACM INFO MSR (0x13A) raw: 0x%016llx\n", acm_info.raw);
|
||||
LOG(" NEM status: %u\n", acm_info.nem_enabled);
|
||||
LOG(" TPM type: %s\n", tpm_type[acm_info.tpm_type]);
|
||||
LOG(" TPM succes: %u\n", acm_info.tpm_success);
|
||||
LOG(" TPM success: %u\n", acm_info.tpm_success);
|
||||
LOG(" FACB: %u\n", acm_info.facb);
|
||||
LOG(" measured boot: %u\n", acm_info.measured_boot);
|
||||
LOG(" verified boot: %u\n", acm_info.verified_boot);
|
||||
|
|
|
|||
|
|
@ -668,7 +668,7 @@ bool stm_check_stm_image(void *stm_image, uint32_t stm_imagesize)
|
|||
/*
|
||||
* This function return BIOS STM resource.
|
||||
* Produced by SmmStm.
|
||||
* Comsumed by SmmMpService when Init.
|
||||
* Consumed by SmmMpService when Init.
|
||||
*
|
||||
* @return BIOS STM resource
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ static struct acm_info_table *find_info_table(const void *ptr)
|
|||
}
|
||||
|
||||
/**
|
||||
* Validate that the provided ACM is useable on this platform.
|
||||
* Validate that the provided ACM is usable on this platform.
|
||||
*/
|
||||
static int validate_acm(const void *ptr)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ static void clear_memory(void *unused)
|
|||
__func__, (void *)pgtbl, (void *)vmem_addr);
|
||||
}
|
||||
|
||||
/* Now clear all useable DRAM */
|
||||
/* Now clear all usable DRAM */
|
||||
memranges_each_entry(r, &mem) {
|
||||
if (range_entry_tag(r) != BM_MEM_RAM)
|
||||
continue;
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ uint32_t tpm_extend_pcr(int pcr, enum vb2_hash_algorithm digest_algo,
|
|||
const char *name);
|
||||
|
||||
/**
|
||||
* Issue a TPM_Clear and reenable/reactivate the TPM.
|
||||
* Issue a TPM_Clear and re-enable/reactivate the TPM.
|
||||
* @return TPM_SUCCESS on success. If not a tpm error is returned
|
||||
*/
|
||||
uint32_t tpm_clear_and_reenable(void);
|
||||
|
|
|
|||
|
|
@ -273,7 +273,7 @@ uint32_t tlcl_self_test_full(void)
|
|||
uint32_t tlcl_lock_nv_write(uint32_t index)
|
||||
{
|
||||
struct tpm2_response *response;
|
||||
/* TPM Wll reject attempts to write at non-defined index. */
|
||||
/* TPM Will reject attempts to write at non-defined index. */
|
||||
struct tpm2_nv_write_lock_cmd nv_wl = {
|
||||
.nvIndex = HR_NV_INDEX + index,
|
||||
};
|
||||
|
|
@ -372,7 +372,7 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size,
|
|||
if (!response)
|
||||
return TPM_E_NO_DEVICE;
|
||||
|
||||
/* Map TPM2 retrun codes into common vboot represenation. */
|
||||
/* Map TPM2 return codes into common vboot representation. */
|
||||
switch (response->hdr.tpm_code) {
|
||||
case TPM2_RC_SUCCESS:
|
||||
return TPM_SUCCESS;
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ int tpm_marshal_command(TPM_CC command, const void *tpm_command_body,
|
|||
* tpm_unmarshal_response
|
||||
*
|
||||
* Given a buffer received from the TPM in response to a certain command,
|
||||
* deserialize the buffer into the expeced response structure.
|
||||
* deserialize the buffer into the expected response structure.
|
||||
*
|
||||
* struct tpm2_response is a union of all possible responses.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue