src/mainboard to src/security: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/amd/bilby/devicetree.cb

@@ -127,7 +127,7 @@ chip soc/amd/picasso
 		.flash_ch_en = 0,
 	}"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_OFF"
 	register "gpp_clk_config[1]" = "GPP_CLK_OFF"
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ"

src/mainboard/amd/mandolin/variants/cereme/devicetree.cb

@@ -118,7 +118,7 @@ chip soc/amd/picasso
 		.flash_ch_en = 0,
 	}"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ"

src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb

@@ -118,7 +118,7 @@ chip soc/amd/picasso
 		.flash_ch_en = 0,
 	}"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ"

src/mainboard/asrock/b75pro3-m/devicetree.cb

@@ -129,7 +129,7 @@ chip northbridge/intel/sandybridge
 						irq 0xe9 = 0x02
 						irq 0xf0 = 0x20
 					end
-					device pnp 2e.b off	end		# HWM, front pannel LED
+					device pnp 2e.b off	end		# HWM, front panel LED
 					device pnp 2e.d on end		# VID
 					device pnp 2e.e off end		# CIR WAKE-UP
 					device pnp 2e.f on end		# GPIO Push-Pull or Open-drain

src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb

@@ -105,7 +105,7 @@ chip northbridge/intel/x4x		# Northbridge
 						irq 0xe9 = 0x02
 						irq 0xf0 = 0x20
 					end
-					device pnp 2e.b on		# HWM, front pannel LED
+					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0x290
 						io 0x62 = 0x200
 						irq 0x70 = 0

src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb

@@ -99,7 +99,7 @@ chip northbridge/intel/x4x		# Northbridge
 					device pnp 2e.a on		# ACPI
 						irq 0xe4 = 0x10 # Power dram during s3
 					end
-					device pnp 2e.b on		# HWM, front pannel LED
+					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0x290
 						irq 0x70 = 0
 					end

src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb

@@ -100,7 +100,7 @@ chip northbridge/intel/x4x		# Northbridge
 					device pnp 2e.a on		# ACPI
 						irq 0xe4 = 0x10 # Power dram during s3
 					end
-					device pnp 2e.b on		# HWM, front pannel LED
+					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0x290
 						irq 0x70 = 0
 					end

src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb

@@ -34,7 +34,7 @@ chip northbridge/intel/x4x		# Northbridge
 						irq 0x70 = 0
 						irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
 					end
-					device pnp 2e.b on		# HWM, front pannel LED
+					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0x290
 						irq 0x70 = 0
 					end

src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c

@@ -106,9 +106,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 			{ 1, 0, 0x0080 }, /* USB3 front internal header */
 			{ 1, 0, 0x0080 }, /* USB3 front internal header */
 			{ 1, 1, 0x0080 }, /* USB3 ETH top connector */
-			{ 1, 1, 0x0080 }, /* USB3 ETH botton connector */
+			{ 1, 1, 0x0080 }, /* USB3 ETH bottom connector */
 			{ 1, 2, 0x0080 }, /* USB2 PS2 top connector */
-			{ 1, 2, 0x0080 }, /* USB2 PS2 botton connector */
+			{ 1, 2, 0x0080 }, /* USB2 PS2 bottom connector */
 			{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
 			{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
 			{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */

src/mainboard/emulation/qemu-armv7/memlayout.ld

@@ -18,7 +18,7 @@
  * with -bios option which neatly puts coreboot into flash and so payloads
  * can find CBFS and we don't risk overwriting CBFS.
  *
- * Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash
+ * Prior to Jul 2014 qemu aliased 0 to beginning of RAM instead of flash
  * and -bios was unusable as $pc pointed to 0 which was zero-filled as a
  * workaround we suggested using -kernel but this still had all the issues
  * of having fake-ROM in RAM. In fact it was even worse as fake ROM ends

src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h

@@ -2,7 +2,7 @@
 
 /*
  * These are the qemu firmware config interface defines and structs.
- * Copied over from qemu soure tree,
+ * Copied over from qemu source tree,
  * include/standard-headers/linux/qemu_fw_cfg.h and modified accordingly.
  */
 #ifndef FW_CFG_IF_H

src/mainboard/emulation/qemu-q35/bootblock.c

@@ -16,7 +16,7 @@ static void bootblock_northbridge_init(void)
 	 * MCFG. This code also assumes that bootblock_northbridge_init() is
 	 * the first thing called in the non-asm boot block code. The final
 	 * assumption is that no assembly code is using the
-	 * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
+	 * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
 	 *
 	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
 	 * 4GiB.

src/mainboard/facebook/fbg1701/ramstage.c

@@ -181,7 +181,7 @@ static const struct edp_data b101uan08_table[] = {
 	{6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00} },
 	{6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} },
 	{6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} },
-	/* Additional Settng for eDP */
+	/* Additional Setting for eDP */
 	{3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} },
 	{3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} },
 	/* DPRX CAD Register Setting */

src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex

@@ -39,7 +39,7 @@
 #	4 SDRAM CHIP Density and Banks
 #		bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
 #		bits[6:4]: 0 = 3 (8 banks)
-#		bits[7]: reserverd
+#		bits[7]: reserved
 05
 
 #	5 SDRAM Addressing

src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex

@@ -39,7 +39,7 @@
 #	4 SDRAM CHIP Density and Banks
 #		bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
 #		bits[6:4]: 0 = 3 (8 banks)
-#		bits[7]: reserverd
+#		bits[7]: reserved
 05
 
 #	5 SDRAM Addressing

src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex

@@ -38,7 +38,7 @@
 #	4 SDRAM CHIP Density and Banks
 #		bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
 #		bits[6:4]: 0 = 3 (8 banks)
-#		bits[7]: reserverd
+#		bits[7]: reserved
 04
 
 #	5 SDRAM Addressing

src/mainboard/google/daisy/mainboard.c

@@ -202,7 +202,7 @@ static void setup_storage(void)
 
 static void gpio_init(void)
 {
-	/* Set up the I2C busses. */
+	/* Set up the I2C buses. */
 	exynos_pinmux_i2c0();
 	exynos_pinmux_i2c1();
 	exynos_pinmux_i2c2();
@@ -222,7 +222,7 @@ static void gpio_init(void)
 	gpio_direction_output(GPIO_X17, 1);
 	gpio_direction_output(GPIO_X15, 1);
 
-	/* Set up the I2S busses. */
+	/* Set up the I2S buses. */
 	exynos_pinmux_i2s0();
 	exynos_pinmux_i2s1();
 }

src/mainboard/google/foster/bct/jtag.cfg

@@ -1,5 +1,5 @@
 #
-# Set DebugCtrl to 1 to reenable Jtag
+# Set DebugCtrl to 1 to re-enable Jtag
 #
 DebugCtrl = 0;
 #

src/mainboard/google/gru/pwm_regulator.c

@@ -60,7 +60,7 @@ int pwm_enum_to_pwm_number[] = {
 void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt)
 {
 	int duty_ns, voltage_max, voltage_min;
-	int voltage = millivolt * 10; /* for higer calculation accuracy */
+	int voltage = millivolt * 10; /* for higher calculation accuracy */
 	int pwm_number = pwm_enum_to_pwm_number[pwm];
 
 	voltage_min = pwm_design_voltage[pwm][0];

src/mainboard/google/guybrush/variants/baseboard/devicetree.cb

@@ -80,7 +80,7 @@ chip soc/amd/cezanne
 	register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR
 	register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ"

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -44,7 +44,7 @@ chip soc/intel/cannonlake
 	register "tcc_offset" = "10"	# TCC of 90C
 	# Unlock GPIO pads
 	register "PchUnlockGpioPads" = "1"
-	# SD card WP pin confguration
+	# SD card WP pin configuration
 	register "ScsSdCardWpPinEnabled" = "0"
 
 	# NOTE: if any variant wants to override this value, use the same format

src/mainboard/google/kahlee/mainboard.c

@@ -117,7 +117,7 @@ static void mainboard_init(void *chip_info)
 	gpios = variant_gpio_table(&num_gpios);
 	gpio_configure_pads(gpios, num_gpios);
 
-	/* Initialize i2c busses that were not initialized in bootblock */
+	/* Initialize i2c buses that were not initialized in bootblock */
 	i2c_soc_init();
 
 	/* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */

src/mainboard/google/oak/mainboard.c

@@ -231,7 +231,7 @@ static void display_startup(void)
 static void mainboard_init(struct device *dev)
 {
 	/* TP_SHIFT_EN: Enables the level shifter for I2C bus 4 (TPAD), which
-	 * also contains the PS8640 eDP brige and the USB hub.
+	 * also contains the PS8640 eDP bridge and the USB hub.
 	 */
 	if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5)
 		mt6391_gpio_output(MT6391_KP_ROW2, 1);

src/mainboard/google/octopus/mainboard.c

@@ -69,7 +69,7 @@ static void gpio_modification_by_ssfc(struct pad_config *table, size_t num)
 	/*
 	 * Currently we only have the case of RT5682 as the second source. And
 	 * in case of Ampton which used RT5682 as the default source, it didn't
-	 * provide override_table right now so it will be returned ealier since
+	 * provide override_table right now so it will be returned earlier since
 	 * table above is NULL.
 	 */
 	if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682)

src/mainboard/google/octopus/variants/baseboard/gpio.c

@@ -324,7 +324,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
 
 	/*
-	 * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak
+	 * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak
 	 * pull-up for proper operation. Since there is no external pull present
 	 * on this platform, configure an internal weak pull-up.
 	 */

src/mainboard/google/octopus/variants/yorp/gpio.c

@@ -25,7 +25,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
 
 	/*
-	 * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak
+	 * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak
 	 * pull-up for proper operation. Since there is no external pull present
 	 * on this platform, configure an internal weak pull-up.
 	 */

src/mainboard/google/peach_pit/mainboard.c

@@ -330,7 +330,7 @@ static void setup_storage(void)
 
 static void gpio_init(void)
 {
-	/* Set up the I2C busses. */
+	/* Set up the I2C buses. */
 	exynos_pinmux_i2c2();
 	exynos_pinmux_i2c4();
 	exynos_pinmux_i2c7();

src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl

@@ -262,7 +262,7 @@ Scope (\_SB.PCI0.I2C2)
 		 * AX1V: Auxiliary LDO1 VR voltage value
 		 * AX2V: Auxiliary LDO2 VR voltage value
 		 * ACVA: Analog LDO VR voltage
-		 * DCVA: Core buck VR volatage
+		 * DCVA: Core buck VR voltage
 		 */
 		OperationRegion (PWR2, 0xB1, Zero, 0x0100)
 		Field (PWR2, DWordAcc, NoLock, Preserve)

src/mainboard/google/smaug/bct/jtag.cfg

@@ -1,5 +1,5 @@
 #
-# Set JtagCtrl to 1 to reenable Jtag
+# Set JtagCtrl to 1 to re-enable Jtag
 #
 JtagCtrl = 0;
 #

src/mainboard/google/stout/dsdt.asl

@@ -17,7 +17,7 @@ DefinitionBlock(
 	#include "acpi/platform.asl"
 	#include "acpi/mainboard.asl"
 
-	// Thermal handeler
+	// Thermal handler
 	#include "acpi/thermal.asl"
 
 	// global NVS and variables

src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb

@@ -21,7 +21,7 @@ chip soc/amd/picasso
 	}"
 
 	# Start : OPN Performance Configuration
-	# (Configuratin that is common for all variants)
+	# (Configuration that is common for all variants)
 	# For the below fields, 0 indicates use SOC default
 
 	# PROCHOT_L de-assertion Ramp Time
@@ -232,7 +232,7 @@ chip soc/amd/picasso
 
 	register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
 	register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD

src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb

@@ -19,7 +19,7 @@ chip soc/amd/picasso
 	}"
 
 	# Start : OPN Performance Configuration
-	# (Configuratin that is common for all variants)
+	# (Configuration that is common for all variants)
 	# For the below fields, 0 indicates use SOC default
 
 	# PROCHOT_L de-assertion Ramp Time
@@ -230,7 +230,7 @@ chip soc/amd/picasso
 
 	register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
 	register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
 	register "gpp_clk_config[2]" = "GPP_CLK_OFF"

src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h

@@ -49,7 +49,7 @@ void variant_touchscreen_update(void);
 void variant_pcie_gpio_configure(void);
 
 /* Per variant FSP-S initialization, default implementation in baseboard and
- * overrideable by the variant. */
+ * overridable by the variant. */
 void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs,
 				      size_t *dxio_num,
 				      const fsp_ddi_descriptor **ddi_descs,

src/mainboard/intel/dcp847ske/devicetree.cb

@@ -81,7 +81,7 @@ chip northbridge/intel/sandybridge
 					device pnp 4e.609 off end	# GPIO6
 					device pnp 4e.709 off end	# GPIO7
 					device pnp 4e.a on end		# ACPI
-					device pnp 4e.b on		# HWM, front pannel LED
+					device pnp 4e.b on		# HWM, front panel LED
 						io 0x60 = 0xa30
 						io 0x62 = 0 # unused
 					end

src/mainboard/intel/dg41wv/devicetree.cb

@@ -129,7 +129,7 @@ chip northbridge/intel/x4x		# Northbridge
 						irq 0xe4 = 0x10 # Power dram during s3
 						irq 0xe6 = 0x8c
 					end
-					device pnp 2e.b on		# HWM, front pannel LED
+					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0xa00
 						irq 0x70 = 0
 					end

src/mainboard/intel/kblrvp/acpi/mipi_camera.asl

@@ -108,7 +108,7 @@ Scope (\_SB.PCI0.I2C2)
 		 * AX1V: Auxiliary LDO1 VR voltage value
 		 * AX2V: Auxiliary LDO2 VR voltage value
 		 * ACVA: Analog LDO VR voltage
-		 * DCVA: Core buck VR volatage
+		 * DCVA: Core buck VR voltage
 		 */
 		OperationRegion (PWR2, 0xB1, Zero, 0x0100)
 		Field (PWR2, DWordAcc, NoLock, Preserve)
@@ -613,7 +613,7 @@ Scope (\_SB.PCI0.I2C3)
 		 * AX1V: Auxiliary LDO1 VR voltage value
 		 * AX2V: Auxiliary LDO2 VR voltage value
 		 * ACVA: Analog LDO VR voltage
-		 * DCVA: Core buck VR volatage
+		 * DCVA: Core buck VR voltage
 		 */
 		OperationRegion (PWR2, 0xB1, Zero, 0x0100)
 		Field (PWR2, DWordAcc, NoLock, Preserve)

src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c

@@ -104,7 +104,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 }
 
 /**
- * @brief Customer Overides Memory Table
+ * @brief Customer Overrides Memory Table
  *
  * Platform Specific Overriding Table allows IBV/OEM to pass in platform
  * information to AGESA

src/mainboard/lenovo/s230u/acpi/ec.asl

@@ -144,7 +144,7 @@ Device (EC0)
 		^HKEY.MHKQ (0x6040)
 	}
 
-	/* Lid openend */
+	/* Lid opened */
 	Method (_Q2A, 0, NotSerialized)
 	{
 		LIDS = 1

src/mainboard/lippert/frontrunner-af/dsdt.asl

@@ -535,7 +535,7 @@ DefinitionBlock (
 				 * The Secondary bus range for PCI0 lets the system
 				 * know what bus values are allowed on the downstream
 				 * side of this PCI bus if there is a PCI-PCI bridge.
-				 * PCI busses can have 256 secondary busses which
+				 * PCI buses can have 256 secondary buses which
 				 * range from [0-0xFF] but they do not need to be
 				 * sequential.
 				 */

src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex

@@ -39,7 +39,7 @@
 #	4 SDRAM CHIP Density and Banks
 #		bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
 #		bits[6:4]: 0 = 3 (8 banks)
-#		bits[7]: reserverd
+#		bits[7]: reserved
 05
 
 #	5 SDRAM Addressing

src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex

@@ -39,7 +39,7 @@
 #	4 SDRAM CHIP Density and Banks
 #		bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
 #		bits[6:4]: 0 = 3 (8 banks)
-#		bits[7]: reserverd
+#		bits[7]: reserved
 05
 
 #	5 SDRAM Addressing

src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex

@@ -38,7 +38,7 @@
 #	4 SDRAM CHIP Density and Banks
 #		bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
 #		bits[6:4]: 0 = 3 (8 banks)
-#		bits[7]: reserverd
+#		bits[7]: reserved
 04
 
 #	5 SDRAM Addressing

src/mainboard/protectli/vault_bsw/romstage.c

@@ -12,7 +12,7 @@
 void mainboard_after_memory_init(void)
 {
 	/*
-	 * FSP enables internal UART. Disable it and reenable Super I/O UART to
+	 * FSP enables internal UART. Disable it and re-enable Super I/O UART to
 	 * prevent loss of debug information on serial.
 	 */
 	pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0);

src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl

@@ -32,7 +32,7 @@ Device (EC)
 		BIF0,   16,
 		BDCP,   16, // BAT Design Capacity
 		BFCP,   16, // BAT Full Capacity
-		BRCH,   16, // BAT Rechargable
+		BRCH,   16, // BAT Rechargeable
 		BDVT,   16, // BAT Design Voltage
 		BIF5,   16,
 		BIF6,   16,

src/mainboard/roda/rk9/acpi/ec.asl

@@ -42,7 +42,7 @@ Device(EC0)
 		FDDI,   1, // floppy on lpt indicator?
 		LIDC,   1, // LID switch
 			Offset(0xd0),
-		TCPU,   8, // T_CPU in deg Celcius
+		TCPU,   8, // T_CPU in deg Celsius
 			Offset(0xd6),
 		/* exact purpose of these three is guessed,
 		   but it's something about cooling */

src/mainboard/roda/rk9/acpi/thermal.asl

@@ -4,7 +4,7 @@
 
 Scope (\_TZ)
 {
-	/* degree Celcius to deci-Kelvin (ACPI temperature unit) */
+	/* degree Celsius to deci-Kelvin (ACPI temperature unit) */
 	Method(C2dK, 1) {
 		Add (2732, Multiply (Arg0, 10), Local0)
 		Return (Local0)

src/northbridge/intel/haswell/northbridge.c

@@ -35,7 +35,7 @@ static const char *northbridge_acpi_name(const struct device *dev)
 }
 
 /*
- * TODO: We could determine how many PCIe busses we need in the bar.
+ * TODO: We could determine how many PCIe buses we need in the bar.
  *       For now, that number is hardcoded to a max of 64.
  */
 static struct device_operations pci_domain_ops = {

src/northbridge/intel/i945/Kconfig

@@ -63,7 +63,7 @@ config MAXIMUM_SUPPORTED_FREQUENCY
 config CHECK_SLFRCS_ON_RESUME
 	def_bool n
 	help
-	  On some boards it may be neccessary to hard reset early
+	  On some boards it may be necessary to hard reset early
 	  during resume from S3 if the SLFRCS register indicates that
 	  a memory channel is not guaranteed to be in self-refresh.
 	  On other boards the check always creates a false positive,

src/northbridge/intel/ironlake/bootblock.c

@@ -22,7 +22,7 @@ void bootblock_early_northbridge_init(void)
 {
 	/*
 	 * The QuickPath bus number is the topmost bus number, as per the value
-	 * of the SAD_PCIEXBAR register. The register defaults to 256 busses on
+	 * of the SAD_PCIEXBAR register. The register defaults to 256 buses on
 	 * reset. Thus, hardcode the bus number when first setting up PCIEXBAR.
 	 */
 	const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1);

src/northbridge/intel/sandybridge/raminit_common.c

@@ -2437,7 +2437,7 @@ int aggressive_write_training(ramctr_timing *ctrl)
 	if (enable_iosav_opt)
 		mchbar_write32(MCMNTS_SPARE, 1);
 
-	printram("Aggresive write training:\n");
+	printram("Aggressive write training:\n");
 
 	for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) {
 		FOR_ALL_POPULATED_CHANNELS {

src/security/intel/cbnt/logging.c

@@ -123,7 +123,7 @@ void intel_cbnt_log_registers(void)
 	LOG("SACM INFO MSR (0x13A) raw: 0x%016llx\n", acm_info.raw);
 	LOG("  NEM status:              %u\n", acm_info.nem_enabled);
 	LOG("  TPM type:                %s\n", tpm_type[acm_info.tpm_type]);
-	LOG("  TPM succes:              %u\n", acm_info.tpm_success);
+	LOG("  TPM success:             %u\n", acm_info.tpm_success);
 	LOG("  FACB:                    %u\n", acm_info.facb);
 	LOG("  measured boot:           %u\n", acm_info.measured_boot);
 	LOG("  verified boot:           %u\n", acm_info.verified_boot);

src/security/intel/stm/SmmStm.c

@@ -668,7 +668,7 @@ bool stm_check_stm_image(void *stm_image, uint32_t stm_imagesize)
 /*
  *  This function return BIOS STM resource.
  *  Produced by SmmStm.
- *  Comsumed by SmmMpService when Init.
+ *  Consumed by SmmMpService when Init.
  *
  *  @return BIOS STM resource
  */

src/security/intel/txt/common.c

@@ -150,7 +150,7 @@ static struct acm_info_table *find_info_table(const void *ptr)
 }
 
 /**
- * Validate that the provided ACM is useable on this platform.
+ * Validate that the provided ACM is usable on this platform.
  */
 static int validate_acm(const void *ptr)
 {

src/security/memory/memory_clear.c

@@ -98,7 +98,7 @@ static void clear_memory(void *unused)
 		__func__, (void *)pgtbl, (void *)vmem_addr);
 	}
 
-	/* Now clear all useable DRAM */
+	/* Now clear all usable DRAM */
 	memranges_each_entry(r, &mem) {
 		if (range_entry_tag(r) != BM_MEM_RAM)
 			continue;

src/security/tpm/tspi.h

@@ -55,7 +55,7 @@ uint32_t tpm_extend_pcr(int pcr, enum vb2_hash_algorithm digest_algo,
 			const char *name);
 
 /**
- * Issue a TPM_Clear and reenable/reactivate the TPM.
+ * Issue a TPM_Clear and re-enable/reactivate the TPM.
  * @return TPM_SUCCESS on success. If not a tpm error is returned
  */
 uint32_t tpm_clear_and_reenable(void);

src/security/tpm/tss/tcg-2.0/tss.c

@@ -273,7 +273,7 @@ uint32_t tlcl_self_test_full(void)
 uint32_t tlcl_lock_nv_write(uint32_t index)
 {
 	struct tpm2_response *response;
-	/* TPM Wll reject attempts to write at non-defined index. */
+	/* TPM Will reject attempts to write at non-defined index. */
 	struct tpm2_nv_write_lock_cmd nv_wl = {
 		.nvIndex = HR_NV_INDEX + index,
 	};
@@ -372,7 +372,7 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size,
 	if (!response)
 		return TPM_E_NO_DEVICE;
 
-	/* Map TPM2 retrun codes into common vboot represenation. */
+	/* Map TPM2 return codes into common vboot representation. */
 	switch (response->hdr.tpm_code) {
 	case TPM2_RC_SUCCESS:
 		return TPM_SUCCESS;

src/security/tpm/tss/tcg-2.0/tss_marshaling.h

@@ -28,7 +28,7 @@ int tpm_marshal_command(TPM_CC command, const void *tpm_command_body,
  * tpm_unmarshal_response
  *
  * Given a buffer received from the TPM in response to a certain command,
- * deserialize the buffer into the expeced response structure.
+ * deserialize the buffer into the expected response structure.
  *
  * struct tpm2_response is a union of all possible responses.
  *