soc/amd/mendocino: Add UPD to support USB3 force to gen1 by port
Add UPD usb3_port_force_gen1 to support USB3 port force to gen1 BUG=b:273841155 BRANCH=skyrim TEST=Build, verify USB3 port setting to gen1. Change-Id: Iaa476f56cf10588d7de2203deca4122958c00783 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -13,6 +13,16 @@
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#include <types.h>
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#include <types.h>
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#include <vendorcode/amd/fsp/mendocino/FspUsb.h>
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#include <vendorcode/amd/fsp/mendocino/FspUsb.h>
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/* force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc */
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union __packed usb3_force_gen1 {
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struct {
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uint8_t xhci0_port0:1;
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uint8_t xhci1_port0:1;
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uint8_t xhci1_port1:1;
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} ports;
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uint8_t usb3_port_force_gen1_en;
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};
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struct soc_amd_mendocino_config {
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struct soc_amd_mendocino_config {
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struct soc_amd_common_config common_config;
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struct soc_amd_common_config common_config;
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u8 i2c_scl_reset;
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u8 i2c_scl_reset;
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@ -163,6 +173,10 @@ struct soc_amd_mendocino_config {
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/* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal
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/* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal
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Integrity is highly recommended. */
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Integrity is highly recommended. */
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uint8_t dxio_tx_vboost_enable;
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uint8_t dxio_tx_vboost_enable;
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/* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */
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union usb3_force_gen1 usb3_port_force_gen1;
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};
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};
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#endif /* MENDOCINO_CHIP_H */
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#endif /* MENDOCINO_CHIP_H */
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@ -174,4 +174,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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fsp_fill_pcie_ddi_descriptors(mcfg);
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fsp_fill_pcie_ddi_descriptors(mcfg);
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fsp_assign_ioapic_upds(mcfg);
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fsp_assign_ioapic_upds(mcfg);
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mb_pre_fspm(mcfg);
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mb_pre_fspm(mcfg);
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mcfg->fch_usb_3_port_force_gen1 = config->usb3_port_force_gen1.usb3_port_force_gen1_en;
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}
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}
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