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soc/amd/mendocino: Add UPD to support USB3 force to gen1 by port 

Add UPD usb3_port_force_gen1 to support USB3 port force to gen1

BUG=b:273841155
BRANCH=skyrim
TEST=Build, verify USB3 port setting to gen1.

Change-Id: Iaa476f56cf10588d7de2203deca4122958c00783
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Huang 2023-03-22 13:18:03 +08:00 committed by Felix Held
parent 292e673276
commit 509321f5a8
2 changed files with 16 additions and 0 deletions
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14
src/soc/amd/mendocino/chip.h
View File

@ -13,6 +13,16 @@
#include <types.h>
#include <vendorcode/amd/fsp/mendocino/FspUsb.h>
/* force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc */
union __packed usb3_force_gen1 {
struct {
uint8_t xhci0_port0:1;
uint8_t xhci1_port0:1;
uint8_t xhci1_port1:1;
} ports;
uint8_t usb3_port_force_gen1_en;
};
struct soc_amd_mendocino_config {
struct soc_amd_common_config common_config;
u8 i2c_scl_reset;
@ -163,6 +173,10 @@ struct soc_amd_mendocino_config {
/* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal
Integrity is highly recommended. */
uint8_t dxio_tx_vboost_enable;
/* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */
union usb3_force_gen1 usb3_port_force_gen1;
};
#endif /* MENDOCINO_CHIP_H */

2
src/soc/amd/mendocino/fsp_m_params.c
View File

@ -174,4 +174,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
fsp_fill_pcie_ddi_descriptors(mcfg);
fsp_assign_ioapic_upds(mcfg);
mb_pre_fspm(mcfg);
mcfg->fch_usb_3_port_force_gen1 = config->usb3_port_force_gen1.usb3_port_force_gen1_en;
}