soc/intel/fsp_baytrail: Get rid of device_t
Use of device_t has been abandoned in ramstage. Change-Id: I52534b67cd3cd8489925941f45a756b3d430e072 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
parent
4aec34005d
commit
509edac717
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@ -499,7 +499,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
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acpigen_pop_len();
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}
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void generate_cpu_entries(device_t device)
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void generate_cpu_entries(struct device *device)
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{
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int core;
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int pcontrol_blk = get_pmbase(), plen = 6;
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@ -553,7 +553,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
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return current;
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}
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unsigned long southcluster_write_acpi_tables(device_t device,
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unsigned long southcluster_write_acpi_tables(struct device *device,
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unsigned long current,
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struct acpi_rsdp *rsdp)
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{
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@ -581,7 +581,7 @@ unsigned long southcluster_write_acpi_tables(device_t device,
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return current;
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}
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void southcluster_inject_dsdt(device_t device)
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void southcluster_inject_dsdt(struct device *device)
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{
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global_nvs_t *gnvs;
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@ -21,7 +21,7 @@
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include "chip.h"
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static void pci_domain_set_resources(device_t dev)
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static void pci_domain_set_resources(struct device *dev)
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{
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assign_resources(dev->link_list);
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}
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@ -42,7 +42,7 @@ static struct device_operations cpu_bus_ops = {
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.scan_bus = NULL,
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};
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static void enable_dev(device_t dev)
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static void enable_dev(struct device *dev)
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{
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printk(BIOS_DEBUG, "enable_dev(%s, %d)\n",
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dev_name(dev), dev->path.type);
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@ -73,7 +73,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = {
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.init = soc_init,
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};
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static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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@ -42,7 +42,7 @@ static const struct reg_script core_msr_script[] = {
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REG_SCRIPT_END
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};
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static void baytrail_core_init(device_t cpu)
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static void baytrail_core_init(struct device *cpu)
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{
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printk(BIOS_DEBUG, "Init BayTrail core.\n");
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@ -164,7 +164,7 @@ static const struct mp_ops mp_ops = {
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.post_mp_init = enable_smis,
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};
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void baytrail_init_cpus(device_t dev)
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void baytrail_init_cpus(struct device *dev)
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{
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struct bus *cpu_bus = dev->link_list;
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@ -74,24 +74,24 @@ static const struct reg_script gfx_post_vbios_script[] = {
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REG_SCRIPT_END
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};
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static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
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static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)
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{
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reg_script_run_on_dev(dev, ops);
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}
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static void gfx_pre_vbios_init(device_t dev)
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static void gfx_pre_vbios_init(struct device *dev)
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{
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printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
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gfx_run_script(dev, gpu_pre_vbios_script);
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}
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static void gfx_post_vbios_init(device_t dev)
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static void gfx_post_vbios_init(struct device *dev)
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{
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printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
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gfx_run_script(dev, gfx_post_vbios_script);
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}
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static void gfx_init(device_t dev)
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static void gfx_init(struct device *dev)
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{
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/* Pre VBIOS Init */
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gfx_pre_vbios_init(dev);
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@ -100,7 +100,7 @@ static int wait_for_idle(char *base_adr)
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*/
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int i2c_init(unsigned bus)
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{
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device_t dev;
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struct device *dev;
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int base_adr[7] = {I2C0_MEM_BASE, I2C1_MEM_BASE, I2C2_MEM_BASE,
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I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE,
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I2C6_MEM_BASE};
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@ -166,7 +166,7 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr,
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{
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int i = 0;
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char *base_ptr = NULL;
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device_t dev;
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struct device *dev;
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unsigned int val;
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int stat;
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@ -225,7 +225,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr,
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{
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int i;
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char *base_ptr;
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device_t dev;
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struct device *dev;
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unsigned int val;
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int stat;
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@ -28,10 +28,10 @@ unsigned long acpi_madt_irq_overrides(unsigned long current);
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void acpi_init_gnvs(global_nvs_t *gnvs);
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#ifndef __SIMPLE_DEVICE__
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unsigned long southcluster_write_acpi_tables(device_t device,
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unsigned long southcluster_write_acpi_tables(struct device *device,
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unsigned long current,
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struct acpi_rsdp *rsdp);
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void southcluster_inject_dsdt(device_t device);
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void southcluster_inject_dsdt(struct device *device);
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#endif
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#endif /* _BAYTRAIL_ACPI_H_ */
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@ -56,7 +56,7 @@ void rangeley_early_initialization(void);
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int soc_silicon_revision(void);
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int soc_silicon_type(void);
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int soc_silicon_supported(int type, int rev);
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void soc_enable(device_t dev);
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void soc_enable(struct device *dev);
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/* debugging functions */
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void print_pci_devices(void);
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@ -21,10 +21,10 @@
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/* The baytrail_init_pre_device() function is called prior to device
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* initialization, but it's after console and cbmem has been reinitialized. */
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void baytrail_init_pre_device(void);
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void baytrail_init_cpus(device_t dev);
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void baytrail_init_cpus(struct device *dev);
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void set_max_freq(void);
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void southcluster_enable_dev(device_t dev);
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void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
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void southcluster_enable_dev(struct device *dev);
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void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
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extern struct pci_operations soc_pci_ops;
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@ -41,7 +41,7 @@
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#define FIRMWARE_REG_BASE_C0 0x144000
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#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
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static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
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static void assign_device_nvs(struct device *dev, u32 *field, unsigned index)
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{
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struct resource *res;
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@ -50,7 +50,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
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*field = res->base;
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}
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static void lpe_enable_acpi_mode(device_t dev)
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static void lpe_enable_acpi_mode(struct device *dev)
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{
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static const struct reg_script ops[] = {
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/* Disable PCI interrupt, enable Memory and Bus Master */
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@ -83,7 +83,7 @@ static void lpe_enable_acpi_mode(device_t dev)
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reg_script_run_on_dev(dev, ops);
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}
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static void setup_codec_clock(device_t dev)
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static void setup_codec_clock(struct device *dev)
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{
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uint32_t reg;
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u32 *clk_reg;
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@ -121,7 +121,7 @@ static void setup_codec_clock(device_t dev)
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write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
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}
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static void lpe_stash_firmware_info(device_t dev)
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static void lpe_stash_firmware_info(struct device *dev)
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{
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struct resource *res;
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struct resource *mmio;
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@ -147,7 +147,7 @@ static void lpe_stash_firmware_info(device_t dev)
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}
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}
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static void lpe_init(device_t dev)
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static void lpe_init(struct device *dev)
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{
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struct soc_intel_fsp_baytrail_config *config = dev->chip_info;
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@ -159,7 +159,7 @@ static void lpe_init(device_t dev)
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lpe_enable_acpi_mode(dev);
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}
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static void lpe_read_resources(device_t dev)
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static void lpe_read_resources(struct device *dev)
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{
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pci_dev_read_resources(dev);
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@ -29,7 +29,7 @@
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#include "chip.h"
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static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
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static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
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{
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struct reg_script ops[] = {
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/* Disable PCI interrupt, enable Memory and Bus Master */
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reg_script_run_on_dev(dev, ops);
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}
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static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
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static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg)
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{
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struct reg_script ops[] = {
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REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg,
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reg_script_run_on_dev(dev, ops);
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}
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static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
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static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
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{
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*iosf_reg = -1;
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*nvs_index = -1;
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@ -119,7 +119,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
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}
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}
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static void i2c_disable_resets(device_t dev)
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static void i2c_disable_resets(struct device *dev)
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{
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/* Release the I2C devices from reset. */
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static const struct reg_script ops[] = {
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@ -146,7 +146,7 @@ static void i2c_disable_resets(device_t dev)
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}
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}
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static void lpss_init(device_t dev)
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static void lpss_init(struct device *dev)
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{
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struct soc_intel_fsp_baytrail_config *config = dev->chip_info;
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int iosf_reg, nvs_index;
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@ -88,7 +88,7 @@ uint32_t nc_read_top_of_low_memory(void)
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static int get_pcie_bar(u32 *base)
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{
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device_t dev;
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struct device *dev;
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u32 pciexbar_reg;
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*base = 0;
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@ -123,7 +123,7 @@ static int add_fixed_resources(struct device *dev, int index)
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return index;
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}
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static void mc_add_dram_resources(device_t dev)
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static void mc_add_dram_resources(struct device *dev)
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{
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u32 bmbound, bsmmrrl;
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int index = 0;
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@ -166,7 +166,7 @@ static void mc_add_dram_resources(device_t dev)
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index = add_fixed_resources(dev, index);
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}
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static void nc_read_resources(device_t dev)
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static void nc_read_resources(struct device *dev)
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{
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u32 pcie_config_base;
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int buses;
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@ -185,7 +185,7 @@ static void nc_read_resources(device_t dev)
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mc_add_dram_resources(dev);
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}
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static void nc_enable(device_t dev)
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static void nc_enable(struct device *dev)
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{
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print_fsp_info();
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}
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@ -73,7 +73,7 @@ static const char *stepping_str[] = {
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static void fill_in_pattrs(void)
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{
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device_t dev;
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struct device *dev;
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msr_t msr;
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struct pattrs *attrs = (struct pattrs *)pattrs_get();
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@ -50,12 +50,12 @@
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typedef struct soc_intel_fsp_baytrail_config config_t;
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static inline void
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add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
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add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)
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{
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mmio_resource(dev, i, addr >> 10, size >> 10);
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}
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static void sc_add_mmio_resources(device_t dev)
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static void sc_add_mmio_resources(struct device *dev)
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{
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add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
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add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
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@ -167,8 +167,8 @@ static void sc_enable_serial_irqs(struct device *dev)
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*/
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static void write_pci_config_irqs(void)
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{
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device_t irq_dev;
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device_t targ_dev;
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struct device *irq_dev;
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struct device *targ_dev;
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uint8_t int_line = 0;
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uint8_t original_int_pin = 0;
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uint8_t new_int_pin = 0;
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@ -261,7 +261,7 @@ static void write_pci_config_irqs(void)
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printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
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}
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static void sc_pirq_init(device_t dev)
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static void sc_pirq_init(struct device *dev)
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{
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int i, j;
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int pirq;
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@ -324,7 +324,7 @@ static inline int io_range_in_default(int base, int size)
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* Note: this function assumes there is no overlap with the default LPC device's
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* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
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*/
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static void sc_add_io_resource(device_t dev, int base, int size, int index)
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static void sc_add_io_resource(struct device *dev, int base, int size, int index)
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{
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struct resource *res;
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@ -338,7 +338,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index)
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IORESOURCE_FIXED;
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}
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static void sc_add_io_resources(device_t dev)
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static void sc_add_io_resources(struct device *dev)
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{
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struct resource *res;
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u8 io_index = 0;
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@ -360,7 +360,7 @@ static void sc_add_io_resources(device_t dev)
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sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
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}
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static void sc_read_resources(device_t dev)
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static void sc_read_resources(struct device *dev)
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{
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/* Get the normal PCI resources of this device. */
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pci_dev_read_resources(dev);
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@ -415,7 +415,7 @@ static void sc_init(struct device *dev)
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*/
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/* Set bit in function disable register to hide this device. */
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static void sc_disable_devfn(device_t dev)
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static void sc_disable_devfn(struct device *dev)
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{
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u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
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u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
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@ -463,7 +463,7 @@ static void sc_disable_devfn(device_t dev)
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}
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}
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static inline void set_d3hot_bits(device_t dev, int offset)
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static inline void set_d3hot_bits(struct device *dev, int offset)
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{
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uint32_t reg8;
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printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
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@ -475,7 +475,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
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/* Parts of the audio subsystem are powered by the HDA device. Therefore, one
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* cannot put HDA into D3Hot. Instead perform this workaround to make some of
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* the audio paths work for LPE audio. */
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static void hda_work_around(device_t dev)
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static void hda_work_around(struct device *dev)
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{
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u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
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@ -492,7 +492,7 @@ static void hda_work_around(device_t dev)
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
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}
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static int place_device_in_d3hot(device_t dev)
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static int place_device_in_d3hot(struct device *dev)
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{
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unsigned offset;
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|
@ -569,7 +569,7 @@ static int place_device_in_d3hot(device_t dev)
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}
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/* Common PCI device function disable. */
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void southcluster_enable_dev(device_t dev)
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void southcluster_enable_dev(struct device *dev)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
|
|
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Reference in New Issue