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mb/google/nissa/var/pujjo: Add FW_CONFIG probe for Pujjoteen disable 

bypass power

Add FW_CONFIG probe to separate ext fivr settings for Pujjoteen
and others(Pujjo and Pujjoflex)

BUG=b:242663554
TEST=Boot to OS and verify that ext_fivr_settings are set based on
fw_config.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I6bb6d1701c55459cf331dd2f3ffe07f91bca2fa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
This commit is contained in:
Leo Chou 2022-08-18 18:17:57 +08:00 committed by Martin L Roth
parent d6bf000a0e
commit 50b45d35f0
3 changed files with 40 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/brya/variants/pujjo/Makefile.inc
View File

@ -4,4 +4,5 @@ bootblock-y += gpio.c
romstage-y += gpio.c romstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
ramstage-y += variant.c
ramstage-y += gpio.c ramstage-y += gpio.c

17
src/mainboard/google/brya/variants/pujjo/overridetree.cb
View File

@ -24,6 +24,10 @@ fw_config
field AUDIO 12 14 field AUDIO 12 14
option ALC1019_ALC5682IVS 0 option ALC1019_ALC5682IVS 0
end end
field EXT_VR 15
option EXT_VR_PRESENT 0
option EXT_VR_ABSENT 1
end
end end
@ -55,19 +59,10 @@ chip soc/intel/alderlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN
# Configure external V1P05/Vnn/VnnSx Rails # FIVR configurations for Pujjoteen are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented.
register "ext_fivr_settings" = "{ register "ext_fivr_settings" = "{
.configure_ext_fivr = 1, .configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
.v1p05_voltage_mv = 1050,
.vnn_voltage_mv = 780,
.vnn_sx_voltage_mv = 1050,
.v1p05_icc_max_ma = 500,
.vnn_icc_max_ma = 500,
}" }"
# Intel Common SoC Config # Intel Common SoC Config

33
src/mainboard/google/brya/variants/pujjo/variant.c Normal file
View File

@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <fw_config.h>
#include <baseboard/variants.h>
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
// Configure external V1P05/Vnn/VnnSx Rails for Pujjo, Pujjoflex
if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) {
config->ext_fivr_settings.configure_ext_fivr = 1;
config->ext_fivr_settings.v1p05_enable_bitmap =
FIVR_ENABLE_ALL_SX;
config->ext_fivr_settings.vnn_enable_bitmap =
FIVR_ENABLE_ALL_SX;
config->ext_fivr_settings.vnn_sx_enable_bitmap =
FIVR_ENABLE_ALL_SX;
config->ext_fivr_settings.v1p05_supported_voltage_bitmap =
FIVR_VOLTAGE_NORMAL;
config->ext_fivr_settings.vnn_supported_voltage_bitmap =
FIVR_VOLTAGE_MIN_ACTIVE;
config->ext_fivr_settings.v1p05_voltage_mv = 1050;
config->ext_fivr_settings.vnn_voltage_mv = 780;
config->ext_fivr_settings.vnn_sx_voltage_mv = 1050;
config->ext_fivr_settings.v1p05_icc_max_ma = 500;
config->ext_fivr_settings.vnn_icc_max_ma = 500;
}
}