From 50b74b2a270b85bdd843dd7925c21596534f07b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Mon, 1 Oct 2018 09:45:49 +0200 Subject: [PATCH] arch/riscv: Update comment about mstatus initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit coreboot does not set up virtual memory anymore. Change-Id: I231af07b2988e8362d1cdd606ce889fb31136ff1 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/28831 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Hug Reviewed-by: Ronald G. Minnich --- src/arch/riscv/bootblock.S | 2 +- src/arch/riscv/ramstage.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 95e1923ce2..277c3910c0 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -66,7 +66,7 @@ _hart_zero: # clear any pending interrupts csrwi mip, 0 - # set up the mstatus register for VM + # set up the mstatus register call mstatus_init tail main diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 906215ca01..c721a126c4 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -43,7 +43,7 @@ _start: csrwi mip, 0 call exit_car - # set up the mstatus register for VM + # set up the mstatus register call mstatus_init tail main