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nb/intel/sandybridge: add and use memory thermal configuration registers 

Change-Id: I96efeadcc7d22bc8453645f6a0884d82edf3aec6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Felix Held 2019-12-30 20:41:54 +01:00
parent f54ae3875f
commit 50b7ed2bbe
2 changed files with 6 additions and 3 deletions
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6
src/northbridge/intel/sandybridge/raminit_common.c
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@ -3164,9 +3164,9 @@ void final_registers(ramctr_timing * ctrl)
} }
} }
MCHBAR32(0x5880) = 0xca9171e5; MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5;
MCHBAR32_AND_OR(0x5888, ~0xffffff, 0xe4d5d0); MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0xffffff, 0xe4d5d0);
MCHBAR32_AND(0x58a8, ~0x1f); MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f);
FOR_ALL_CHANNELS FOR_ALL_CHANNELS
MCHBAR32_AND_OR(TC_RFP_C0 + 0x400 * channel, ~0x30000, 1 << 16); MCHBAR32_AND_OR(TC_RFP_C0 + 0x400 * channel, ~0x30000, 1 << 16);

3
src/northbridge/intel/sandybridge/sandybridge.h
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@ -137,6 +137,9 @@ enum platform_type {
#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */
#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ #define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */
#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ #define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */
#define MEM_TRML_ESTIMATION_CONFIG 0x5880
#define MEM_TRML_THRESHOLDS_CONFIG 0x5888
#define MEM_TRML_INTERRUPT 0x58a8
#define MC_BIOS_REQ 0x5e00 #define MC_BIOS_REQ 0x5e00
#define MC_BIOS_DATA 0x5e04 #define MC_BIOS_DATA 0x5e04
#define SSKPD 0x5d14 /* 16bit (scratchpad) */ #define SSKPD 0x5d14 /* 16bit (scratchpad) */