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mb/google/dedede/var/cappy2: Add USB2 PHY parameters 

This change adds fine-tuned USB2 PHY parameters for cappy2.

BUG=b:199485217
TEST=Built and verified USB2 eye diagram test result

Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I2aac29e8bba0bf3eff91898ded7561b6211af789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Sunwei Li 2021-09-10 16:01:30 +08:00 committed by Felix Held
parent 86f0df4ca2
commit 50ba6dfec8
1 changed files with 24 additions and 1 deletions
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25
src/mainboard/google/dedede/variants/cappy2/overridetree.cb
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@ -44,7 +44,30 @@ chip soc/intel/jasperlake
register "disable_external_bypass_vr" = "1" # Does not support external vnn power rail
# USB Port Configuration
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-C
register "usb2_ports[2]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A
register "usb2_ports[5]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Camera
device domain 0 on
device pci 14.0 on