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AGESA fam14: Sanitize headerfile 

This file is only static defines.

Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18585
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Kyösti Mälkki 2017-03-05 14:07:32 +02:00
parent c3c407c62c
commit 50bb68f2b6
11 changed files with 0 additions and 49 deletions
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4
src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
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@ -16,10 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2

5
src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
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@ -16,11 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <cpu/amd/agesa/s3_resume.h>
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2

4
src/mainboard/amd/south_station/PlatformGnbPcieComplex.h
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@ -16,10 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2

4
src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
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@ -16,10 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2

4
src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
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@ -16,10 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2

5
src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h
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@ -16,11 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <cpu/amd/agesa/s3_resume.h>
/*
* GNB GPP Port4
* GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable

5
src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h
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@ -17,11 +17,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <cpu/amd/agesa/s3_resume.h>
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2

3
src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
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@ -17,9 +17,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include <vendorcode/amd/agesa/f14/AGESA.h>
#include <amdlib.h>
/**
* @brief Graphic NorthBridge (GNB) General Purpose Port (GPP)
*

5
src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h
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@ -16,11 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <cpu/amd/agesa/s3_resume.h>
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2

5
src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h
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@ -16,11 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <cpu/amd/agesa/s3_resume.h>
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2

5
src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h
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@ -17,11 +17,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <cpu/amd/agesa/s3_resume.h>
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2