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intel/skylake: unconditionally set SPI controller BAR 

The setting of the SPI controller BAR was conditional
on the nominal frequency being set. Therefore, that doesn't
mean the SPI BAR is set on all boots. Move the setting of
the BAR in the southbridge_bootblock_init() which is called
prioer to cpu_bootblock_init().

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Confirmed spibar is always set on glados.

Change-Id: Ia58447d70f5e39a4336d4d08593f143332de833a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 56fff7c25c2eb0ccd90e08f71c064b83c66640f8
Original-Change-Id: I1e0cff783f4b072b80589a3a84703a262b86be3a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/319461
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13587
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin 2015-12-16 17:11:27 -06:00 committed by Patrick Georgi
parent 4121f9e555
commit 50c3ba24d4
2 changed files with 22 additions and 16 deletions
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16
src/soc/intel/skylake/bootblock/cpu.c
View File

@ -74,25 +74,9 @@ static void bootblock_mdelay(int ms)
static void set_pch_cpu_strap(u8 flex_ratio)
{
device_t dev = PCH_DEV_SPI;
uint8_t *spibar = (void *)SPI_BASE_ADDRESS;
u32 ssl, ssms, soft_reset_data;
u8 pcireg;
/* Assign Resources to SPI Controller */
/* Clear BIT 1-2 SPI Command Register */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
pci_write_config8(dev, PCI_COMMAND, pcireg);
/* Program Temporary BAR for SPI */
pci_write_config32(dev, PCI_BASE_ADDRESS_0,
SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
/* Enable Bus Master and MMIO Space */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config8(dev, PCI_COMMAND, pcireg);
/* Set Strap Lock Disable */
ssl = read32(spibar + SPIBAR_RESET_LOCK);

22
src/soc/intel/skylake/bootblock/pch.c
View File

@ -30,7 +30,29 @@ static void enable_spi_prefetch(void)
pci_write_config8(PCH_DEV_SPI, 0xdc, reg8);
}
static void enable_spibar(void)
{
device_t dev = PCH_DEV_SPI;
u8 pcireg;
/* Assign Resources to SPI Controller */
/* Clear BIT 1-2 SPI Command Register */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
pci_write_config8(dev, PCI_COMMAND, pcireg);
/* Program Temporary BAR for SPI */
pci_write_config32(dev, PCI_BASE_ADDRESS_0,
SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
/* Enable Bus Master and MMIO Space */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config8(dev, PCI_COMMAND, pcireg);
}
static void bootblock_southbridge_init(void)
{
enable_spibar();
enable_spi_prefetch();
}