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AGESA fam12 fam14 fam15: Sanitize BiosCallOuts headers 

Change-Id: Ic08f1f2fdbcf6164eb1a0330f9134da3fdb978d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7114
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Kyösti Mälkki 2014-10-18 07:51:03 +03:00
parent a1ebbc42ad
commit 50c9637e15
26 changed files with 44 additions and 91 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/amd/dinar/BiosCallOuts.c
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@ -29,18 +29,6 @@
#include <southbridge/amd/cimx/sb700/smbus_spd.h>
#ifndef SB_GPIO_REG01
#define SB_GPIO_REG01 1
#endif
#ifndef SB_GPIO_REG24
#define SB_GPIO_REG24 24
#endif
#ifndef SB_GPIO_REG27
#define SB_GPIO_REG27 27
#endif
#ifdef __PRE_RAM__
/* This define is used when selecting the appropriate socket for the SPD read
* because this is a multi-socket design.

8
src/mainboard/amd/dinar/BiosCallOuts.h
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@ -24,13 +24,5 @@
#include <northbridge/amd/agesa/family15/fam15_callouts.h>
#define SB_GPIO_REG02 2
#define SB_GPIO_REG09 9
#define SB_GPIO_REG10 10
#define SB_GPIO_REG15 15
#define SB_GPIO_REG17 17
#define SB_GPIO_REG21 21
#define SB_GPIO_REG25 25
#define SB_GPIO_REG28 28
#endif //_BIOS_CALLOUT_H_

1
src/mainboard/amd/inagua/BiosCallOuts.c
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@ -22,6 +22,7 @@
#include "BiosCallOuts.h"
#include "heapManager.h"
#include "SB800.h"
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
#include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);

8
src/mainboard/amd/inagua/BiosCallOuts.h
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@ -24,13 +24,5 @@
#include <northbridge/amd/agesa/family14/fam14_callouts.h>
#define SB_GPIO_REG02 2
#define SB_GPIO_REG09 9
#define SB_GPIO_REG10 10
#define SB_GPIO_REG15 15
#define SB_GPIO_REG17 17
#define SB_GPIO_REG21 21
#define SB_GPIO_REG25 25
#define SB_GPIO_REG28 28
#endif //_BIOS_CALLOUT_H_

1
src/mainboard/amd/inagua/PlatformGnbPcie.c
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@ -18,7 +18,6 @@
*/
#include "PlatformGnbPcieComplex.h"
#include "BiosCallOuts.h"
#include <string.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>

1
src/mainboard/amd/persimmon/PlatformGnbPcie.c
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@ -18,7 +18,6 @@
*/
#include "PlatformGnbPcieComplex.h"
#include "BiosCallOuts.h"
#include <string.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>

1
src/mainboard/amd/south_station/BiosCallOuts.c
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@ -22,6 +22,7 @@
#include "BiosCallOuts.h"
#include "heapManager.h"
#include "SB800.h"
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
#include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);

9
src/mainboard/amd/south_station/BiosCallOuts.h
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@ -24,13 +24,4 @@
#include <northbridge/amd/agesa/family14/fam14_callouts.h>
#define SB_GPIO_REG02 2
#define SB_GPIO_REG09 9
#define SB_GPIO_REG10 10
#define SB_GPIO_REG15 15
#define SB_GPIO_REG17 17
#define SB_GPIO_REG21 21
#define SB_GPIO_REG25 25
#define SB_GPIO_REG28 28
#endif //_BIOS_CALLOUT_H_

1
src/mainboard/amd/south_station/PlatformGnbPcie.c
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@ -18,7 +18,6 @@
*/
#include "PlatformGnbPcieComplex.h"
#include "BiosCallOuts.h"
#include <string.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>

13
src/mainboard/amd/torpedo/BiosCallOuts.c
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@ -25,18 +25,7 @@
#include "heapManager.h"
#include "Hudson-2.h"
#include <stdlib.h>
#ifndef SB_GPIO_REG01
#define SB_GPIO_REG01 1
#endif
#ifndef SB_GPIO_REG24
#define SB_GPIO_REG24 24
#endif
#ifndef SB_GPIO_REG27
#define SB_GPIO_REG27 27
#endif
#include <southbridge/amd/cimx/sb700/gpio_oem.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);

5
src/mainboard/amd/torpedo/BiosCallOuts.h
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@ -24,9 +24,4 @@
#include <northbridge/amd/agesa/family12/fam12_callouts.h>
// These registers are not defined in cimx/SB900/Hudson-2.h
#define SB_GPIO_REG02 2
#define SB_GPIO_REG15 15
#define SB_GPIO_REG25 25
#endif //_BIOS_CALLOUT_H_

1
src/mainboard/amd/torpedo/PlatformGnbPcie.c
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@ -18,7 +18,6 @@
*/
#include "PlatformGnbPcieComplex.h"
#include "BiosCallOuts.h"
#include <string.h>
#include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h>

1
src/mainboard/amd/union_station/BiosCallOuts.c
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@ -22,6 +22,7 @@
#include "BiosCallOuts.h"
#include "heapManager.h"
#include "SB800.h"
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
#include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);

8
src/mainboard/amd/union_station/BiosCallOuts.h
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@ -24,13 +24,5 @@
#include <northbridge/amd/agesa/family14/fam14_callouts.h>
#define SB_GPIO_REG02 2
#define SB_GPIO_REG09 9
#define SB_GPIO_REG10 10
#define SB_GPIO_REG15 15
#define SB_GPIO_REG17 17
#define SB_GPIO_REG21 21
#define SB_GPIO_REG25 25
#define SB_GPIO_REG28 28
#endif //_BIOS_CALLOUT_H_

1
src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c
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@ -24,7 +24,6 @@
#include "heapManager.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include "BiosCallOuts.h"
#include <string.h>

1
src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
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@ -19,7 +19,6 @@
*/
#include "PlatformGnbPcieComplex.h"
#include "BiosCallOuts.h"
#include <string.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>

2
src/mainboard/lippert/frontrunner-af/BiosCallOuts.c
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@ -20,6 +20,8 @@
#include "AGESA.h"
#include "amdlib.h"
#include "BiosCallOuts.h"
#include "SB800.h"
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
#include "heapManager.h"
#include <stdlib.h>

10
src/mainboard/lippert/frontrunner-af/BiosCallOuts.h
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@ -22,15 +22,5 @@
#include <northbridge/amd/agesa/def_callouts.h>
#include <northbridge/amd/agesa/family14/fam14_callouts.h>
#include "SB800.h"
/* FCH GPIO access helpers */
#define FCH_IOMUX(gpio_nr) (*(u8*)(ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr)))
#define FCH_GPIO(gpio_nr) (*(volatile u8*)(ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr)))
static inline u8 fch_gpio_state(unsigned int gpio_nr)
{
return FCH_GPIO(gpio_nr) >> 7;
}
#endif //_BIOS_CALLOUT_H_

1
src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c
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@ -23,7 +23,6 @@
#include "heapManager.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include "BiosCallOuts.h"
#include <string.h>

1
src/mainboard/lippert/frontrunner-af/mainboard.c
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@ -31,6 +31,7 @@
#include <cpu/amd/mtrr.h>
#include "SBPLATFORM.h"
#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
/* Init SIO GPIOs. */
#define SIO_RUNTIME_BASE 0x0E00

2
src/mainboard/lippert/toucan-af/BiosCallOuts.c
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@ -20,6 +20,8 @@
#include "AGESA.h"
#include "amdlib.h"
#include "BiosCallOuts.h"
#include "SB800.h"
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
#include "heapManager.h"
#include <stdlib.h>

11
src/mainboard/lippert/toucan-af/BiosCallOuts.h
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@ -22,16 +22,5 @@
#include <northbridge/amd/agesa/def_callouts.h>
#include <northbridge/amd/agesa/family14/fam14_callouts.h>
#include "SB800.h"
/* FCH GPIO access helpers */
#define FCH_IOMUX(gpio_nr) (*(u8*)(ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr)))
#define FCH_PMIO(reg_nr) (*(u8*)(ACPI_MMIO_BASE+PMIO_BASE+(reg_nr)))
#define FCH_GPIO(gpio_nr) (*(volatile u8*)(ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr)))
static inline u8 fch_gpio_state(unsigned int gpio_nr)
{
return FCH_GPIO(gpio_nr) >> 7;
}
#endif //_BIOS_CALLOUT_H_

1
src/mainboard/lippert/toucan-af/PlatformGnbPcie.c
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@ -23,7 +23,6 @@
#include "heapManager.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include "BiosCallOuts.h"
#include <string.h>

1
src/mainboard/lippert/toucan-af/mainboard.c
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@ -31,6 +31,7 @@
#include <cpu/amd/mtrr.h>
#include "SBPLATFORM.h"
#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
/* Write data block to slave on SMBUS0. */
#define SMB0_STATUS ((SMBUS0_BASE_ADDRESS) + 0)

11
src/southbridge/amd/cimx/sb700/gpio_oem.h Normal file
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@ -0,0 +1,11 @@
#ifndef _CIMX_SB_GPIO_OEM_H_
#define _CIMX_SB_GPIO_OEM_H_
#define SB_GPIO_REG01 1
#define SB_GPIO_REG02 2
#define SB_GPIO_REG15 15
#define SB_GPIO_REG24 24
#define SB_GPIO_REG25 25
#define SB_GPIO_REG27 27
#endif

23
src/southbridge/amd/cimx/sb800/gpio_oem.h Normal file
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@ -0,0 +1,23 @@
#ifndef _CIMX_SB_GPIO_OEM_H_
#define _CIMX_SB_GPIO_OEM_H_
#define SB_GPIO_REG02 2
#define SB_GPIO_REG09 9
#define SB_GPIO_REG10 10
#define SB_GPIO_REG15 15
#define SB_GPIO_REG17 17
#define SB_GPIO_REG21 21
#define SB_GPIO_REG25 25
#define SB_GPIO_REG28 28
/* FCH GPIO access helpers */
#define FCH_IOMUX(gpio_nr) (*(u8*)(ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr)))
#define FCH_PMIO(reg_nr) (*(u8*)(ACPI_MMIO_BASE+PMIO_BASE+(reg_nr)))
#define FCH_GPIO(gpio_nr) (*(volatile u8*)(ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr)))
static inline u8 fch_gpio_state(unsigned int gpio_nr)
{
return FCH_GPIO(gpio_nr) >> 7;
}
#endif