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amd/stoneyridge: Convert BiosRam access to MMIO 

Change the BiosRam read/write functions to use the fixed MMIO range at
0xfed80500.  This is faster than two accesses per byte when using I/O
0xcd4/0xcd5.

Note that BiosRam may only be accessed byte-by-byte.  It does not decode
normally.

Change-Id: I9d8baf2bd5d9d48a87bddfb6a0b86e292a8fdf7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23436
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Marshall Dawson 2018-01-24 21:00:55 -07:00 committed by Martin Roth
parent 7539b8c391
commit 50cc53d0a9
2 changed files with 4 additions and 4 deletions
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1
src/soc/amd/stoneyridge/include/soc/iomap.h
View File

@ -36,6 +36,7 @@
#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
#define APU_SMI_BASE 0xfed80200 #define APU_SMI_BASE 0xfed80200
#define PM_MMIO_BASE 0xfed80300 #define PM_MMIO_BASE 0xfed80300
#define BIOSRAM_MMIO_BASE 0xfed80500
#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 #define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00
#define APU_UART0_BASE 0xfedc6000 #define APU_UART0_BASE 0xfedc6000
#define APU_UART1_BASE 0xfedc8000 #define APU_UART1_BASE 0xfedc8000

7
src/soc/amd/stoneyridge/sb_util.c
View File

@ -78,16 +78,15 @@ void smi_write8(uint8_t offset, uint8_t value)
uint8_t biosram_read8(uint8_t offset) uint8_t biosram_read8(uint8_t offset)
{ {
outb(offset, BIOSRAM_INDEX); return read8((void *)(BIOSRAM_MMIO_BASE + offset));
return inb(BIOSRAM_DATA);
} }
void biosram_write8(uint8_t offset, uint8_t value) void biosram_write8(uint8_t offset, uint8_t value)
{ {
outb(offset, BIOSRAM_INDEX); write8((void *)(BIOSRAM_MMIO_BASE + offset), value);
outb(value, BIOSRAM_DATA);
} }
/* BiosRam may only be accessed a byte at a time */
uint16_t biosram_read16(uint8_t offset) uint16_t biosram_read16(uint8_t offset)
{ {
int i; int i;