soc/intel/skylake: Set PsysPl3 and Pl4
If given a value for PsysPl3 and/or Pl4, set the appropriate MSR. BUG=b:71594855 BRANCH=None TEST=boot up and check MSRs in OS to make sure values are set as expected. Test on Fizz, which will set these values in mainboard. Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
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@ -114,6 +114,8 @@
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#define PKG_POWER_LIMIT_CLAMP (1 << 16)
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#define PKG_POWER_LIMIT_TIME_SHIFT 17
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#define PKG_POWER_LIMIT_TIME_MASK (0x7f)
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#define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24
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#define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f)
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/* SMM save state MSRs */
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#define SMBASE_MSR 0xc20
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#define IEDBASE_MSR 0xc22
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@ -100,6 +100,16 @@ struct soc_intel_skylake_config {
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/* SysPL2 Value in Watts */
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u32 tdp_psyspl2;
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/* SysPL3 Value in Watts */
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u32 tdp_psyspl3;
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/* SysPL3 window size */
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u32 tdp_psyspl3_time;
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/* SysPL3 duty cycle */
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u32 tdp_psyspl3_dutycycle;
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/* PL4 Value in Watts */
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u32 tdp_pl4;
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/*
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* The following fields come from FspUpdVpd.h.
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* These are configuration values that are passed to FSP during
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@ -191,6 +191,38 @@ void set_power_limits(u8 power_limit_1_time)
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wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
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}
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/* Set PsysPl3 */
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if (conf->tdp_psyspl3) {
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limit = rdmsr(MSR_PL3_CONTROL);
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limit.lo = 0;
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printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n",
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conf->tdp_psyspl3);
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limit.lo |= (conf->tdp_psyspl3 * power_unit) &
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PKG_POWER_LIMIT_MASK;
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/* Enable PsysPl3 */
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limit.lo |= PKG_POWER_LIMIT_EN;
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/* set PsysPl3 time window */
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limit.lo |= (conf->tdp_psyspl3_time &
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PKG_POWER_LIMIT_TIME_MASK) <<
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PKG_POWER_LIMIT_TIME_SHIFT;
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/* set PsysPl3 duty cycle */
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limit.lo |= (conf->tdp_psyspl3_dutycycle &
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PKG_POWER_LIMIT_DUTYCYCLE_MASK) <<
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PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;
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wrmsr(MSR_PL3_CONTROL, limit);
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}
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/* Set Pl4 */
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if (conf->tdp_pl4) {
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limit = rdmsr(MSR_VR_CURRENT_CONFIG);
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limit.lo = 0;
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printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n",
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conf->tdp_pl4);
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limit.lo |= (conf->tdp_pl4 * power_unit) &
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PKG_POWER_LIMIT_MASK;
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wrmsr(MSR_VR_CURRENT_CONFIG, limit);
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}
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/* Set DDR RAPL power limit by copying from MMIO to MSR */
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msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
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msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
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@ -36,6 +36,7 @@
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#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
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#define MSR_VR_CURRENT_CONFIG 0x601
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#define MSR_VR_MISC_CONFIG 0x603
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#define MSR_PL3_CONTROL 0x615
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#define MSR_VR_MISC_CONFIG2 0x636
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#define MSR_PP0_POWER_LIMIT 0x638
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#define MSR_PP1_POWER_LIMIT 0x640
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