GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

northbridge/sch: Read the GPU memory from the correct PCI device 

The GGC register which contains the size of memory that is used for GPU
is in PCI device 2,0 and not 0,0. It is set to to 4MiB in
src/mainboard/iwave/iWRainbowG6/romstage.c.

Change-Id: Ie9f1cc60544ecd9cad770f34c83c33564a6129d4
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1628
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Sebastian Andrzej Siewior 2012-10-26 19:01:17 +02:00 committed by Stefan Reinauer
parent 66fa9e2865
commit 50dd47bb58
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/sch/northbridge.c
View File

@ -144,7 +144,7 @@ static void pci_domain_set_resources(device_t dev)
tseg_memory_size = tseg_size * 1024ULL; tseg_memory_size = tseg_size * 1024ULL;
} }
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(2, 0)), GGC);
if (!(reg16 & 2)) { if (!(reg16 & 2)) {
int uma_size = 0; int uma_size = 0;
printk(BIOS_DEBUG, "IGD decoded, subtracting "); printk(BIOS_DEBUG, "IGD decoded, subtracting ");