soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig
New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake has differences compared to Tigerlake. Thus renaming fsp_params.c to fsp_params_tgl.c to point out correct file as per soc selected. Also adding new file for fsp_param_jsl for Jasperlake SoC and currently its the copy of fsp_param_tgl. TODO: update files with correct fsp_params Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37267 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -33,7 +33,8 @@ ramstage-y += cpu.c
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ramstage-y += elog.c
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ramstage-y += espi.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c
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ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c
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ramstage-y += gpio.c
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ramstage-y += graphics.c
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ramstage-y += lockdown.c
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@ -0,0 +1,46 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <fsp/api.h>
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#include <intelblocks/lpss.h>
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#include <soc/ramstage.h>
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static const pci_devfn_t serial_io_dev[] = {
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PCH_DEVFN_I2C0,
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PCH_DEVFN_I2C1,
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PCH_DEVFN_I2C2,
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PCH_DEVFN_I2C3,
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PCH_DEVFN_I2C4,
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PCH_DEVFN_I2C5,
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PCH_DEVFN_GSPI0,
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PCH_DEVFN_GSPI1,
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PCH_DEVFN_GSPI2,
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PCH_DEVFN_UART0,
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PCH_DEVFN_UART1,
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PCH_DEVFN_UART2
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};
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/* UPD parameters to be initialized before SiliconInit */
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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{
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/* TODO: Update with UPD override as FSP matures */
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}
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/* Return list of SOC LPSS controllers */
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const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
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{
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*size = ARRAY_SIZE(serial_io_dev);
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return serial_io_dev;
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}
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@ -13,7 +13,8 @@
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# GNU General Public License for more details.
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#
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romstage-y += fsp_params.c
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romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c
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romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c
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romstage-y += ../../../../cpu/intel/car/romstage.c
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romstage-y += romstage.c
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romstage-y += pch.c
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <fsp/util.h>
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#include <soc/romstage.h>
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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/* TODO: Update with UPD override as FSP matures */
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}
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