soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig

New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake
has differences compared to Tigerlake. Thus renaming fsp_params.c to
fsp_params_tgl.c to point out correct file as per soc selected.

Also adding new file for fsp_param_jsl for Jasperlake SoC and currently
its the copy of fsp_param_tgl.
TODO: update files with correct fsp_params

Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37267
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maulik V Vaghela 2019-11-27 11:49:39 +05:30 committed by Subrata Banik
parent 58ecefb181
commit 50ee91c17c
6 changed files with 72 additions and 2 deletions

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@ -33,7 +33,8 @@ ramstage-y += cpu.c
ramstage-y += elog.c
ramstage-y += espi.c
ramstage-y += finalize.c
ramstage-y += fsp_params.c
ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c
ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += lockdown.c

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@ -0,0 +1,46 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <fsp/api.h>
#include <intelblocks/lpss.h>
#include <soc/ramstage.h>
static const pci_devfn_t serial_io_dev[] = {
PCH_DEVFN_I2C0,
PCH_DEVFN_I2C1,
PCH_DEVFN_I2C2,
PCH_DEVFN_I2C3,
PCH_DEVFN_I2C4,
PCH_DEVFN_I2C5,
PCH_DEVFN_GSPI0,
PCH_DEVFN_GSPI1,
PCH_DEVFN_GSPI2,
PCH_DEVFN_UART0,
PCH_DEVFN_UART1,
PCH_DEVFN_UART2
};
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
/* TODO: Update with UPD override as FSP matures */
}
/* Return list of SOC LPSS controllers */
const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
{
*size = ARRAY_SIZE(serial_io_dev);
return serial_io_dev;
}

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@ -13,7 +13,8 @@
# GNU General Public License for more details.
#
romstage-y += fsp_params.c
romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c
romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c
romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += pch.c

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@ -0,0 +1,22 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <fsp/util.h>
#include <soc/romstage.h>
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
/* TODO: Update with UPD override as FSP matures */
}