GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/alderlake: Add enum for HDA audio configuration 

This change adds an enum to configure the audio related UPDs used for
configuring the audio over HDMI/DP and rename a variable for better
readability.

TEST=On shadowmountain audio sound cards are detected and listed by the
Linux kernel. Audio playback and capture is working fine.

Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Sugnan Prabhu S 2021-03-18 22:08:22 +05:30 committed by Tim Wawrzynczak
parent c1c1ba5582
commit 50f8b4ebdd
5 changed files with 26 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/mainboard/intel/adlrvp/devicetree.cb
View File

@ -171,12 +171,9 @@ chip soc/intel/alderlake
# HD Audio
register "PchHdaDspEnable" = "1"
# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
register "PchHdaIDispLinkTmode" = "2"
# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
register "PchHdaIDispLinkFrequency" = "4"
# Not disconnected/enumerable
register "PchHdaIDispCodecDisconnect" = "0"
register "PchHdaIDispLinkTmode" = "HDA_TMODE_4T"
register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
register "PchHdaIDispCodecEnable" = "1"
register "CnviBtAudioOffload" = "true"

9
src/mainboard/intel/adlrvp/devicetree_m.cb
View File

@ -121,12 +121,9 @@ chip soc/intel/alderlake
# HD Audio
register "PchHdaDspEnable" = "1"
# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
register "PchHdaIDispLinkTmode" = "3"
# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
register "PchHdaIDispLinkFrequency" = "4"
# Not disconnected/enumerable
register "PchHdaIDispCodecDisconnect" = "0"
register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
register "PchHdaIDispCodecEnable" = "1"
# Intel Common SoC Config
register "common_soc_config" = "{

9
src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
View File

@ -111,12 +111,9 @@ chip soc/intel/alderlake
# HD Audio
register "PchHdaDspEnable" = "1"
# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
register "PchHdaIDispLinkTmode" = "3"
# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
register "PchHdaIDispLinkFrequency" = "4"
# Not disconnected/enumerable
register "PchHdaIDispCodecDisconnect" = "0"
register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
register "PchHdaIDispCodecEnable" = "1"
# DP port
register "DdiPortAConfig" = "1" # eDP

19
src/soc/intel/alderlake/chip.h
View File

@ -113,9 +113,22 @@ struct soc_intel_alderlake_config {
/* Audio related */
uint8_t PchHdaDspEnable;
uint8_t PchHdaIDispLinkTmode;
uint8_t PchHdaIDispLinkFrequency;
uint8_t PchHdaIDispCodecDisconnect;
/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
enum {
HDA_TMODE_2T = 0,
HDA_TMODE_4T = 2,
HDA_TMODE_8T = 3,
HDA_TMODE_16T = 4,
} PchHdaIDispLinkTmode;
/* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */
enum {
HDA_LINKFREQ_48MHZ = 3,
HDA_LINKFREQ_96MHZ = 4,
} PchHdaIDispLinkFrequency;
bool PchHdaIDispCodecEnable;
struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS];
struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS];

2
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@ -143,7 +143,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable;
/* Disable all PCIe clock sources by default. And set RP irrelevant clock. */
for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) {