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I just went on a bugfix frenzy and fixed all printk format warnings 

triggered by the AMD 690/SB600 targets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger 2009-03-04 01:06:41 +00:00
parent 4b95ced365
commit 51001fbd81
18 changed files with 26 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -136,7 +136,7 @@ static int lapic_start_cpu(unsigned long apicid)
maxlvt = 4; maxlvt = 4;
for (j = 1; j <= num_starts; j++) { for (j = 1; j <= num_starts; j++) {
printk_spew("Sending STARTUP #%d to %u.\n", j, apicid); printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid);
lapic_read_around(LAPIC_SPIV); lapic_read_around(LAPIC_SPIV);
lapic_write(LAPIC_ESR, 0); lapic_write(LAPIC_ESR, 0);
lapic_read(LAPIC_ESR); lapic_read(LAPIC_ESR);
@ -239,7 +239,7 @@ int start_cpu(device_t cpu)
#warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n" #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n"
#endif #endif
if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) { if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10); printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10);
die("Can not go on\n"); die("Can not go on\n");
} }
stack_end -= sizeof(struct cpu_info); stack_end -= sizeof(struct cpu_info);

2
src/cpu/x86/mtrr/mtrr.c
View File

@ -357,7 +357,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
#endif #endif
} }
/* Allocate an msr */ /* Allocate an msr */
printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek); printk_spew(" Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek);
state->range_startk = basek; state->range_startk = basek;
state->range_sizek = sizek; state->range_sizek = sizek;
} }

2
src/devices/device.c
View File

@ -358,7 +358,7 @@ void compute_allocate_resource(
base += size; base += size;
printk_spew( printk_spew(
"%s %02x * [0x%08Lx - 0x%08Lx] %s\n", "%s %02lx * [0x%08Lx - 0x%08Lx] %s\n",
dev_path(dev), dev_path(dev),
resource->index, resource->index,
resource->base, resource->base,

2
src/lib/malloc.c
View File

@ -27,7 +27,7 @@ void *malloc(size_t size)
{ {
void *p; void *p;
MALLOCDBG(("%s Enter, size %d, free_mem_ptr %p\n", __func__, size, free_mem_ptr)); MALLOCDBG(("%s Enter, size %ld, free_mem_ptr 0x%08lx\n", __func__, size, free_mem_ptr));
if (size < 0) if (size < 0)
die("Error! malloc: Size < 0"); die("Error! malloc: Size < 0");
if (free_mem_ptr <= 0) if (free_mem_ptr <= 0)

2
src/mainboard/amd/dbm690t/acpi_tables.c
View File

@ -254,7 +254,7 @@ unsigned long write_acpi_tables(unsigned long start)
memcpy((void *)dsdt, (void *)AmlCode, memcpy((void *)dsdt, (void *)AmlCode,
((acpi_header_t *) AmlCode)->length); ((acpi_header_t *) AmlCode)->length);
current += dsdt->length; current += dsdt->length;
printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length);
/* FADT */ /* FADT */
printk_debug("ACPI: * FADT\n"); printk_debug("ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current; fadt = (acpi_fadt_t *) current;

2
src/mainboard/amd/dbm690t/irq_tables.c
View File

@ -73,7 +73,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15; addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */ /* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr); printk_info("Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); pirq = (void *)(addr);
v = (u8 *) (addr); v = (u8 *) (addr);

8
src/mainboard/amd/dbm690t/mainboard.c
View File

@ -61,7 +61,7 @@ static void enable_onboard_nic()
{ {
u8 byte; u8 byte;
printk_info("enable_onboard_nic.\n"); printk_info("%s.\n", __func__);
/* set index register 0C50h to 13h (miscellaneous control) */ /* set index register 0C50h to 13h (miscellaneous control) */
outb(0x13, 0xC50); /* CMIndex */ outb(0x13, 0xC50); /* CMIndex */
@ -202,7 +202,7 @@ void dbm690t_enable(device_t dev)
struct mainboard_config *mainboard = struct mainboard_config *mainboard =
(struct mainboard_config *)dev->chip_info; (struct mainboard_config *)dev->chip_info;
printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev); printk_info("Mainboard DBM690T Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1) #if (CONFIG_GFXUMA == 1)
msr_t msr, msr2; msr_t msr, msr2;
@ -236,7 +236,7 @@ void dbm690t_enable(device_t dev)
} }
uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base); __func__, uma_memory_size, uma_memory_base);
/* TODO: TOP_MEM2 */ /* TODO: TOP_MEM2 */
@ -256,7 +256,7 @@ int add_mainboard_resources(struct lb_memory *mem)
* in some circumstances we want the memory mentioned as reserved. * in some circumstances we want the memory mentioned as reserved.
*/ */
#if (CONFIG_GFXUMA == 1) #if (CONFIG_GFXUMA == 1)
printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size); uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size); uma_memory_base, uma_memory_size);

2
src/mainboard/amd/pistachio/acpi_tables.c
View File

@ -255,7 +255,7 @@ unsigned long write_acpi_tables(unsigned long start)
((acpi_header_t *) AmlCode)->length); ((acpi_header_t *) AmlCode)->length);
current += dsdt->length; current += dsdt->length;
printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length);
/* FADT */ /* FADT */
printk_debug("ACPI: * FADT\n"); printk_debug("ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current; fadt = (acpi_fadt_t *) current;

2
src/mainboard/amd/pistachio/irq_tables.c
View File

@ -73,7 +73,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15; addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */ /* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr); printk_info("Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); pirq = (void *)(addr);
v = (u8 *) (addr); v = (u8 *) (addr);

8
src/mainboard/amd/pistachio/mainboard.c
View File

@ -61,7 +61,7 @@ static void enable_onboard_nic()
{ {
u8 byte; u8 byte;
printk_info("enable_onboard_nic.\n"); printk_info("%s.\n", __func__);
/* enable GPM8 output */ /* enable GPM8 output */
byte = pm_ioread(0x95); byte = pm_ioread(0x95);
@ -274,7 +274,7 @@ void pistachio_enable(device_t dev)
struct mainboard_config *mainboard = struct mainboard_config *mainboard =
(struct mainboard_config *)dev->chip_info; (struct mainboard_config *)dev->chip_info;
printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev); printk_info("Mainboard Pistachio Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1) #if (CONFIG_GFXUMA == 1)
msr_t msr, msr2; msr_t msr, msr2;
@ -308,7 +308,7 @@ void pistachio_enable(device_t dev)
} }
uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk_info("%s: uma size 0x%08lx, memory start 0x%08lx\n", printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base); __func__, uma_memory_size, uma_memory_base);
/* TODO: TOP_MEM2 */ /* TODO: TOP_MEM2 */
@ -328,7 +328,7 @@ int add_mainboard_resources(struct lb_memory *mem)
* in some circumstances we want the memory mentioned as reserved. * in some circumstances we want the memory mentioned as reserved.
*/ */
#if (CONFIG_GFXUMA == 1) #if (CONFIG_GFXUMA == 1)
printk_info("uma_memory_base=0x%lx, uma_memory_size=0x%lx \n", printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size); uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size); uma_memory_base, uma_memory_size);

2
src/northbridge/amd/amdk8/amdk8_acpi.c
View File

@ -128,7 +128,7 @@ void set_srat_mem(void *gp, struct device *dev, struct resource *res)
basek = resk(res->base); basek = resk(res->base);
sizek = resk(res->size); sizek = resk(res->size);
printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
dev_path(dev), res->index, basek, sizek); dev_path(dev), res->index, basek, sizek);
/* /*
* 0-640K must be on node 0 * 0-640K must be on node 0

2
src/northbridge/amd/amdk8/northbridge.c
View File

@ -473,7 +473,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
limit |= (nodeid & 7); limit |= (nodeid & 7);
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n", printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
__func__, dev_path(dev), link); __func__, dev_path(dev), link);
base |= PCI_IO_BASE_VGA_EN; base |= PCI_IO_BASE_VGA_EN;
} }

2
src/southbridge/amd/rs690/rs690.c
View File

@ -129,7 +129,7 @@ void rs690_enable(device_t dev)
device_t nb_dev = 0, sb_dev = 0; device_t nb_dev = 0, sb_dev = 0;
int dev_ind; int dev_ind;
printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev)); printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!nb_dev) { if (!nb_dev) {

4
src/southbridge/amd/rs690/rs690_gfx.c
View File

@ -121,7 +121,7 @@ static void rs690_internal_gfx_enable(device_t dev)
device_t k8_f0 = 0, k8_f2 = 0; device_t k8_f0 = 0, k8_f2 = 0;
device_t nb_dev = dev_find_slot(0, 0); device_t nb_dev = dev_find_slot(0, 0);
printk_info("rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev, printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
nb_dev); nb_dev);
/* set APERTURE_SIZE, 128M. */ /* set APERTURE_SIZE, 128M. */
@ -417,7 +417,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
struct southbridge_amd_rs690_config *cfg = struct southbridge_amd_rs690_config *cfg =
(struct southbridge_amd_rs690_config *)nb_dev->chip_info; (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
printk_info("rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n", printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
nb_dev, dev, port); nb_dev, dev, port);
/* step 0, REFCLK_SEL, skip A11 revision */ /* step 0, REFCLK_SEL, skip A11 revision */

2
src/southbridge/amd/rs690/rs690_pcie.c
View File

@ -203,7 +203,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
device_t sb_dev; device_t sb_dev;
struct southbridge_amd_rs690_config *cfg = struct southbridge_amd_rs690_config *cfg =
(struct southbridge_amd_rs690_config *)nb_dev->chip_info; (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port); printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
/* init GPP core */ /* init GPP core */
set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8,

2
src/southbridge/amd/sb600/sb600_hda.c
View File

@ -302,7 +302,7 @@ static void hda_init(struct device *dev)
return; return;
base = (u8 *) ((u32)res->base); base = (u8 *) ((u32)res->base);
printk_debug("base = %08x\n", base); printk_debug("base = %p\n", base);
codec_mask = codec_detect(base); codec_mask = codec_detect(base);
if (codec_mask) { if (codec_mask) {

2
src/southbridge/amd/sb600/sb600_sata.c
View File

@ -96,7 +96,7 @@ static void sata_init(struct device *dev)
printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */
printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */
printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */
printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */
/* Program the 2C to 0x43801002 */ /* Program the 2C to 0x43801002 */
dword = 0x43801002; dword = 0x43801002;

2
src/southbridge/amd/sb600/sb600_usb.c
View File

@ -94,7 +94,7 @@ static void usb_init2(struct device *dev)
/* pci_write_config32(dev, 0xf8, dword); */ /* pci_write_config32(dev, 0xf8, dword); */
usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF);
printk_info("usb2_bar0=%x\n", usb2_bar0); printk_info("usb2_bar0=%p\n", usb2_bar0);
/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
dword = 0x00020F00; dword = 0x00020F00;