samus: Minor fixes for P1.9 boards
- Put SSD into reset on transition to S3/S5 to prevent leakage - Fix GPIO number for wlan disable used in smihandler - Enable generic hub driver in libpayload - Fix comment in devicetree about S0ix BUG=chrome-os-partner:28502 BRANCH=None TEST=Build and boot on samus Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203185 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0 Reviewed-on: http://review.coreboot.org/8048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -52,7 +52,7 @@ chip soc/intel/broadwell
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# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013b0000"
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# Enable S0ix
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# Disable S0ix for now
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register "s0ix_enable" = "0"
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device cpu_cluster 0 on
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@ -32,8 +32,8 @@
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#include <broadwell/smm.h>
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#include "ec.h"
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/* GPIO46 controls the WLAN_DISABLE_L signal. */
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#define GPIO_WLAN_DISABLE_L 46
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#define GPIO_SSD_RESET_L 47
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#define GPIO_WLAN_DISABLE_L 42
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#define GPIO_LTE_DISABLE_L 59
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int mainboard_io_trap_handler(int smif)
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@ -103,6 +103,8 @@ void mainboard_smi_sleep(u8 slp_typ)
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1, USB_CHARGE_MODE_DISABLED);
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}
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/* Put SSD in reset to prevent leak. */
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set_gpio(GPIO_SSD_RESET_L, 0);
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/* Prevent leak from standby rail to WLAN rail in S3. */
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set_gpio(GPIO_WLAN_DISABLE_L, 0);
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/* Disable LTE */
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@ -119,6 +121,8 @@ void mainboard_smi_sleep(u8 slp_typ)
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1, USB_CHARGE_MODE_DISABLED);
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}
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/* Put SSD in reset to prevent leak. */
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set_gpio(GPIO_SSD_RESET_L, 0);
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/* Prevent leak from standby rail to WLAN rail in S5. */
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set_gpio(GPIO_WLAN_DISABLE_L, 0);
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/* Disable LTE */
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