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samus: Minor fixes for P1.9 boards 

- Put SSD into reset on transition to S3/S5 to prevent leakage
- Fix GPIO number for wlan disable used in smihandler
- Enable generic hub driver in libpayload
- Fix comment in devicetree about S0ix

BUG=chrome-os-partner:28502
BRANCH=None
TEST=Build and boot on samus

Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203185
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0
Reviewed-on: http://review.coreboot.org/8048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie 2014-06-10 10:05:03 -07:00 committed by Marc Jones
parent ef57a22163
commit 5106b9dbb7
2 changed files with 7 additions and 3 deletions
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2
src/mainboard/google/samus/devicetree.cb
View File

@ -52,7 +52,7 @@ chip soc/intel/broadwell
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013b0000" register "icc_clock_disable" = "0x013b0000"
# Enable S0ix # Disable S0ix for now
register "s0ix_enable" = "0" register "s0ix_enable" = "0"
device cpu_cluster 0 on device cpu_cluster 0 on

8
src/mainboard/google/samus/smihandler.c
View File

@ -32,8 +32,8 @@
#include <broadwell/smm.h> #include <broadwell/smm.h>
#include "ec.h" #include "ec.h"
/* GPIO46 controls the WLAN_DISABLE_L signal. */ #define GPIO_SSD_RESET_L 47
#define GPIO_WLAN_DISABLE_L 46 #define GPIO_WLAN_DISABLE_L 42
#define GPIO_LTE_DISABLE_L 59 #define GPIO_LTE_DISABLE_L 59
int mainboard_io_trap_handler(int smif) int mainboard_io_trap_handler(int smif)
@ -103,6 +103,8 @@ void mainboard_smi_sleep(u8 slp_typ)
1, USB_CHARGE_MODE_DISABLED); 1, USB_CHARGE_MODE_DISABLED);
} }
/* Put SSD in reset to prevent leak. */
set_gpio(GPIO_SSD_RESET_L, 0);
/* Prevent leak from standby rail to WLAN rail in S3. */ /* Prevent leak from standby rail to WLAN rail in S3. */
set_gpio(GPIO_WLAN_DISABLE_L, 0); set_gpio(GPIO_WLAN_DISABLE_L, 0);
/* Disable LTE */ /* Disable LTE */
@ -119,6 +121,8 @@ void mainboard_smi_sleep(u8 slp_typ)
1, USB_CHARGE_MODE_DISABLED); 1, USB_CHARGE_MODE_DISABLED);
} }
/* Put SSD in reset to prevent leak. */
set_gpio(GPIO_SSD_RESET_L, 0);
/* Prevent leak from standby rail to WLAN rail in S5. */ /* Prevent leak from standby rail to WLAN rail in S5. */
set_gpio(GPIO_WLAN_DISABLE_L, 0); set_gpio(GPIO_WLAN_DISABLE_L, 0);
/* Disable LTE */ /* Disable LTE */