soc/intel/tigerlake: Add CPU ID for TGL B0

Reference:
- TGL User Guide #613584 Rev 2.2
- TGL User Guide #605534 Rev 1.0

BRANCH=none
BUG=none
TEST=build and boot tglrvp

Change-Id: I5da80fd4ad321b1ded369c2b6c039b73fcb3773e
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41516
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/cpu/mp_init.c

@@ -73,6 +73,7 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 },
 	{ X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 },
 	{ X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 },
+	{ X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0 },
 	{ X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 },
 	{ X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0},
 	{ 0, 0 },

src/soc/intel/common/block/include/intelblocks/mp_init.h

@@ -41,6 +41,7 @@
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
 #define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
 #define CPUID_TIGERLAKE_A0	0x806c0
+#define CPUID_TIGERLAKE_B0	0x806c1
 #define CPUID_ELKHARTLAKE_A0	0x90660
 
 /*

src/soc/intel/tigerlake/bootblock/report_platform.c

@@ -25,6 +25,7 @@ static struct {
 	const char *name;
 } cpu_table[] = {
 	{ CPUID_TIGERLAKE_A0, "Tigerlake A0" },
+	{ CPUID_TIGERLAKE_B0, "Tigerlake B0" },
 };
 
 static struct {