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RISC-V boards: Remove PAGETABLES section from memlayout.ld 

RISC-V doesn't set up page tables anymore, since commit b26759d703
("arch/riscv: Don't set up virtual memory").

Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Jonathan Neuschäfer 2018-04-17 14:00:34 +02:00 committed by Patrick Georgi
parent 062c729c9b
commit 5135f1184d
4 changed files with 2 additions and 4 deletions
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1
src/arch/riscv/include/arch/memlayout.h
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@ -19,7 +19,6 @@
#define __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H
#define STACK(addr, size) REGION(stack, addr, size, 4096) #define STACK(addr, size) REGION(stack, addr, size, 4096)
#define PAGETABLES(addr, size) REGION(pagetables, addr, size, 4096)
/* TODO: Need to add DMA_COHERENT region like on ARM? */ /* TODO: Need to add DMA_COHERENT region like on ARM? */

1
src/mainboard/emulation/qemu-riscv/memlayout.ld
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@ -24,6 +24,5 @@ SECTIONS
ROMSTAGE(0x20000, 128K) ROMSTAGE(0x20000, 128K)
STACK(0x40000, 0x3ff00) STACK(0x40000, 0x3ff00)
PRERAM_CBMEM_CONSOLE(0x80000, 8K) PRERAM_CBMEM_CONSOLE(0x80000, 8K)
PAGETABLES(0x80000+8K, 60K)
RAMSTAGE(0x100000, 16M) RAMSTAGE(0x100000, 16M)
} }

2
src/mainboard/emulation/spike-riscv/memlayout.ld
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@ -24,7 +24,7 @@ SECTIONS
DRAM_START(START) DRAM_START(START)
BOOTBLOCK(START, 64K) BOOTBLOCK(START, 64K)
STACK(START + 8M, 4K) STACK(START + 8M, 4K)
PAGETABLES(START + 8M + 4K, 60K) /* hole at (START + 8M + 4K, 60K) */
ROMSTAGE(START + 8M + 64K, 128K) ROMSTAGE(START + 8M + 64K, 128K)
PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
RAMSTAGE(START + 8M + 200K, 256K) RAMSTAGE(START + 8M + 200K, 256K)

2
src/mainboard/lowrisc/nexys4ddr/memlayout.ld
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@ -26,6 +26,6 @@ SECTIONS
STACK(START + 8M, 64K) STACK(START + 8M, 64K)
ROMSTAGE(START + 8M + 64K, 128K) ROMSTAGE(START + 8M + 64K, 128K)
PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
PAGETABLES(START + 8M + 200K, 56K) /* hole at (START + 8M + 200K, 56K) */
RAMSTAGE(START + 8M + 256K, 256K) RAMSTAGE(START + 8M + 256K, 256K)
} }