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r4646 enabled early usage of pci_{read,write}_config{8,16,32} 

This allows us to change
dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
        sm_dev->path.pci.devfn, 0x64);

to the much more readable
dword = pci_read_config32(sm_dev, 0x64);

Clean up all PCI operations in mainboards based on AMD 690:
amd/pistachio
amd/dbm690t
technexion/tim8690

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger 2009-09-22 09:43:25 +00:00
parent 00003ae712
commit 513e03bd96
3 changed files with 24 additions and 54 deletions
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32
src/mainboard/amd/dbm690t/mainboard.c
View File

@ -97,32 +97,24 @@ static void enable_onboard_nic()
static void get_ide_dma66() static void get_ide_dma66()
{ {
u8 byte; u8 byte;
/*u32 sm_dev, ide_dev; */ struct device *sm_dev;
device_t sm_dev, ide_dev; struct device *ide_dev;
struct bus pbus;
printk_info("%s.\n", __func__);
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
byte = byte = pci_read_config8(sm_dev, 0xA9);
pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0xA9);
byte |= (1 << 5); /* Set Gpio9 as input */ byte |= (1 << 5); /* Set Gpio9 as input */
pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, pci_write_config8(sm_dev, 0xA9, byte);
sm_dev->path.pci.devfn, 0xA9, byte);
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
byte = byte = pci_read_config8(ide_dev, 0x56);
pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,
ide_dev->path.pci.devfn, 0x56);
byte &= ~(7 << 0); byte &= ~(7 << 0);
if ((1 << 5) & pci_cf8_conf1. if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn,
0xAA))
byte |= 2 << 0; /* mode 2 */ byte |= 2 << 0; /* mode 2 */
else else
byte |= 5 << 0; /* mode 5 */ byte |= 5 << 0; /* mode 5 */
pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary, pci_write_config8(ide_dev, 0x56, byte);
ide_dev->path.pci.devfn, 0x56, byte);
} }
/* /*
@ -133,7 +125,6 @@ static void set_thermal_config()
u8 byte; u8 byte;
u16 word; u16 word;
device_t sm_dev; device_t sm_dev;
struct bus pbus;
/* set ADT 7461 */ /* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@ -156,12 +147,9 @@ static void set_thermal_config()
/* set GPIO 64 to input */ /* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
word = word = pci_read_config16(sm_dev, 0x56);
pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0x56);
word |= 1 << 7; word |= 1 << 7;
pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, pci_write_config16(sm_dev, 0x56, word);
sm_dev->path.pci.devfn, 0x56, word);
/* set GPIO 64 internal pull-up */ /* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0); byte = pm2_ioread(0xf0);

29
src/mainboard/amd/pistachio/mainboard.c
View File

@ -83,7 +83,6 @@ static void set_thermal_config()
u16 word; u16 word;
u32 dword; u32 dword;
device_t sm_dev; device_t sm_dev;
struct bus pbus;
/* set adt7475 */ /* set adt7475 */
ADT7475_write_byte(0x40, 0x04); ADT7475_write_byte(0x40, 0x04);
@ -167,28 +166,19 @@ static void set_thermal_config()
/* GPM5 as GPIO not USB OC */ /* GPM5 as GPIO not USB OC */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
dword = dword = pci_read_config32(sm_dev, 0x64);
pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0x64);
dword |= 1 << 19; dword |= 1 << 19;
pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, pci_write_config32(sm_dev, 0x64, dword);
sm_dev->path.pci.devfn, 0x64, dword);
/* Enable Client Management Index/Data registers */ /* Enable Client Management Index/Data registers */
dword = dword = pci_read_config32(sm_dev, 0x78);
pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0x78);
dword |= 1 << 11; /* Cms_enable */ dword |= 1 << 11; /* Cms_enable */
pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, pci_write_config32(sm_dev, 0x78, dword);
sm_dev->path.pci.devfn, 0x78, dword);
/* MiscfuncEnable */ /* MiscfuncEnable */
byte = byte = pci_read_config8(sm_dev, 0x41);
pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0x41);
byte |= (1 << 5); byte |= (1 << 5);
pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, pci_write_config8(sm_dev, 0x41, byte);
sm_dev->path.pci.devfn, 0x41, byte);
/* set GPM5 as input */ /* set GPM5 as input */
/* set index register 0C50h to 13h (miscellaneous control) */ /* set index register 0C50h to 13h (miscellaneous control) */
@ -228,12 +218,9 @@ static void set_thermal_config()
pm2_iowrite(0x42, byte); pm2_iowrite(0x42, byte);
/* set GPIO 64 to input */ /* set GPIO 64 to input */
word = word = pci_read_config16(sm_dev, 0x56);
pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0x56);
word |= 1 << 7; word |= 1 << 7;
pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, pci_write_config16(sm_dev, 0x56, word);
sm_dev->path.pci.devfn, 0x56, word);
/* set GPIO 64 internal pull-up */ /* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0); byte = pm2_ioread(0xf0);

17
src/mainboard/technexion/tim8690/mainboard.c
View File

@ -59,16 +59,15 @@ static void enable_onboard_nic()
u8 byte; u8 byte;
device_t sm_dev; device_t sm_dev;
struct bus pbus;
printk_info("enable_onboard_nic.\n"); printk_info("enable_onboard_nic.\n");
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
byte= pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x9a); byte = pci_read_config8(sm_dev, 0x9a);
byte |= ( 1 << 7); byte |= ( 1 << 7);
pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x9a,byte); pci_write_config8(sm_dev, 0x9a, byte);
byte=pm_ioread(0x59); byte=pm_ioread(0x59);
@ -76,10 +75,10 @@ static void enable_onboard_nic()
pm_iowrite(0x59,byte); pm_iowrite(0x59,byte);
byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA8); byte = pci_read_config8(sm_dev, 0xA8);
byte |= (1 << 1); //set bit 1 to high byte |= (1 << 1); //set bit 1 to high
pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA8, byte); pci_write_config8(sm_dev, 0xA8, byte);
} }
/* set thermal config /* set thermal config
@ -89,7 +88,6 @@ static void set_thermal_config()
u8 byte; u8 byte;
u16 word; u16 word;
device_t sm_dev; device_t sm_dev;
struct bus pbus;
/* set ADT 7461 */ /* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@ -112,12 +110,9 @@ static void set_thermal_config()
/* set GPIO 64 to input */ /* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
word = word = pci_read_config16(sm_dev, 0x56);
pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0x56);
word |= 1 << 7; word |= 1 << 7;
pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, pci_write_config16(sm_dev, 0x56, word);
sm_dev->path.pci.devfn, 0x56, word);
/* set GPIO 64 internal pull-up */ /* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0); byte = pm2_ioread(0xf0);