diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c
index 871a4366c2..384772374b 100644
--- a/src/northbridge/amd/amdfam10/link_control.c
+++ b/src/northbridge/amd/amdfam10/link_control.c
@@ -25,6 +25,7 @@
 #include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
 #include <cpu/amd/model_10xxx_rev.h>
+#include <types.h>
 
 #include "amdfam10.h"
 
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index bbaec53887..b0a1ab679a 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -32,6 +32,7 @@
 #include <lib.h>
 #include <cbmem.h>
 #include <cpu/amd/model_10xxx_rev.h>
+#include <types.h>
 
 #include "amdfam10.h"
 
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 1d071c1877..a681961be2 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -34,6 +34,7 @@
 #include <cpu/amd/amdfam10_sysconf.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/family_10h-family_15h/ram_calc.h>
+#include <types.h>
 
 #if CONFIG(LOGICAL_CPUS)
 #include <cpu/amd/multicore.h>
diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index 8c33ad8156..cda0a28cef 100644
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -36,6 +36,7 @@
 #include <device/pci_def.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdfam10/amdfam10.h>
+#include <types.h>
 
 /*----------------------------------------------------------------------------
  *			DEFINITIONS AND MACROS
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 74e5234535..42e91b6130 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -43,7 +43,9 @@
 #include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <string.h>
+#include <types.h>
 #include <device/dram/ddr3.h>
+
 #include "s3utils.h"
 #include "mct_d_gcc.h"
 #include "mct_d.h"
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index a78a752052..d991002f5b 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -30,6 +30,8 @@
 #include <spi_flash.h>
 #include <pc80/mc146818rtc.h>
 #include <inttypes.h>
+#include <types.h>
+
 #include "mct_d.h"
 #include "mct_d_gcc.h"
 
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 7aaf016d29..b8042fe46d 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -19,6 +19,7 @@
 #include <arch/cpu.h>
 #include <cpu/amd/msr.h>
 #include <console/console.h>
+#include <types.h>
 
 #include "mcti.h"
 
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 3549b49234..a2de7f0fb0 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -27,6 +27,7 @@
 #include <commonlib/helpers.h>
 #include <cbmem.h>
 #include <southbridge/intel/i82801ix/nvs.h>
+#include <types.h>
 
 #include "drivers/intel/gma/i915_reg.h"
 #include "chip.h"
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 1b2430f849..607fab7602 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -31,6 +31,7 @@
 #include <southbridge/intel/lynxpoint/nvs.h>
 #include <stdlib.h>
 #include <string.h>
+#include <types.h>
 
 #include "chip.h"
 #include "haswell.h"
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 84d9c105d6..f9167dfc97 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <stdint.h>
 #include <stdlib.h>
 #include <cf9_reset.h>
 #include <console/console.h>
@@ -22,9 +21,11 @@
 #include <device/pci_def.h>
 #include <cbmem.h>
 #include <romstage_handoff.h>
-#include "i945.h"
 #include <pc80/mc146818rtc.h>
 #include <southbridge/intel/common/gpio.h>
+#include <types.h>
+
+#include "i945.h"
 
 int i945_silicon_revision(void)
 {
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 1d20533a48..54ff47cc64 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -33,6 +33,7 @@
 #include <commonlib/helpers.h>
 #include <cbmem.h>
 #include <southbridge/intel/i82801gx/nvs.h>
+#include <types.h>
 
 #include "i945.h"
 #include "chip.h"
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index 8c0117f531..087d37e5aa 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -31,6 +31,7 @@
 #include <southbridge/intel/ibexpeak/nvs.h>
 #include <drivers/intel/gma/opregion.h>
 #include <cbmem.h>
+#include <types.h>
 
 #include "chip.h"
 #include "nehalem.h"
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 5b6077f5ea..15d6abb67b 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -30,18 +30,18 @@
 #include <device/device.h>
 #include <halt.h>
 #include <spd.h>
-#include "raminit.h"
-#include "chip.h"
 #include <timestamp.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
 #include <mrc_cache.h>
-
-#include "nehalem.h"
-
 #include <southbridge/intel/ibexpeak/me.h>
 #include <delay.h>
+#include <types.h>
+
+#include "chip.h"
+#include "nehalem.h"
+#include "raminit.h"
 
 #define NORTHBRIDGE PCI_DEV(0, 0, 0)
 #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index 509ab4ee0c..be6a5e27d6 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <stdint.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
@@ -24,6 +23,7 @@
 #include <northbridge/intel/pineview/pineview.h>
 #include <northbridge/intel/pineview/chip.h>
 #include <pc80/mc146818rtc.h>
+#include <types.h>
 
 #define LPC PCI_DEV(0, 0x1f, 0)
 #define D0F0 PCI_DEV(0, 0, 0)
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index 019f7648f0..dd6cb32596 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -23,10 +23,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-
 #include <drivers/intel/gma/i915_reg.h>
-#include "chip.h"
-#include "pineview.h"
 #include <drivers/intel/gma/intel_bios.h>
 #include <drivers/intel/gma/i915.h>
 #include <drivers/intel/gma/opregion.h>
@@ -34,6 +31,10 @@
 #include <cbmem.h>
 #include <pc80/vga.h>
 #include <pc80/vga_io.h>
+#include <types.h>
+
+#include "chip.h"
+#include "pineview.h"
 
 #define GTTSIZE		(512*1024)
 
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 34aec3851b..fd3d34f2de 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <stdint.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
@@ -22,6 +21,8 @@
 #include <device/pci_def.h>
 #include <pc80/mc146818rtc.h>
 #include <romstage_handoff.h>
+#include <types.h>
+
 #include "sandybridge.h"
 
 static void sandybridge_setup_bars(void)
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index cb6782e9b7..1005288fee 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -27,6 +27,7 @@
 #include <drivers/intel/gma/opregion.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <cbmem.h>
+#include <types.h>
 
 #include "chip.h"
 #include "sandybridge.h"
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index f67d61f973..c13ae37fbc 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -30,6 +30,7 @@
 #include <southbridge/intel/common/smbus.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <cpu/x86/msr.h>
+#include <types.h>
 
 #include "raminit_native.h"
 #include "raminit_common.h"
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index c4e8bf1cdd..61731fee3e 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -29,6 +29,7 @@
 #include <drivers/intel/gma/libgfxinit.h>
 #include <pc80/vga.h>
 #include <pc80/vga_io.h>
+#include <types.h>
 
 #include "chip.h"
 #include "drivers/intel/gma/i915_reg.h"
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 7fed1efe26..bd6536ab6f 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -32,6 +32,7 @@
 #include <device/dram/ddr3.h>
 #include <mrc_cache.h>
 #include <timestamp.h>
+#include <types.h>
 
 #include "iomap.h"
 #include "x4x.h"