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soc/intel/alderlake: Add power state thresholds 

This patch adds power state 1/2/3 threshold setting interfaces
and pass the settings to FSP.

BUG=b:229803757
BRANCH=None
TEST=Add psi1threshold and psi2threshold to overridetree.cb and
     enable FSP log to ensure the settings are incorrect.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I0330ede4394ebc2d3d32e4b78297c3cb328660d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Gaggery Tsai 2022-09-08 13:42:08 -07:00 committed by Martin Roth
parent 7125318ac4
commit 517c5a8c54
2 changed files with 12 additions and 0 deletions
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6
src/soc/intel/alderlake/include/soc/vr_config.h
View File

@ -28,6 +28,12 @@ struct vr_config {
/* Thermal Design Current current limit.
Defined in 1/8A units and range is 0-4095. 1000 = 125A. */
uint16_t tdc_currentlimit;
/* Power State 1/2/3 Threshold Current.
Defined in 1/4A units and range is 0-128A */
uint16_t psi1threshold;
uint16_t psi2threshold;
uint16_t psi3threshold;
};
#define VR_CFG_AMP(i) (uint16_t)((i) * 4)

6
src/soc/intel/alderlake/vr_config.c
View File

@ -272,6 +272,12 @@ void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,
s_cfg->DcLoadline[domain] = cfg->dc_loadline;
if (cfg->icc_max)
s_cfg->IccMax[domain] = cfg->icc_max;
if (cfg->psi1threshold)
s_cfg->Psi1Threshold[domain] = cfg->psi1threshold;
if (cfg->psi2threshold)
s_cfg->Psi2Threshold[domain] = cfg->psi2threshold;
if (cfg->psi3threshold)
s_cfg->Psi3Threshold[domain] = cfg->psi3threshold;
s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow;
s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit;
} else {